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board: add Antmicro DDR4 Tester board 

Signed-off-by: Michal Sieron <msieron@antmicro.com>
This commit is contained in:
Michal Sieron 2022-07-27 16:01:27 +02:00 committed by Tomasz Michalak
parent 308e47c5c0
commit 17939d587e
2 changed files with 8 additions and 0 deletions
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7
doc/boards.yml
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@ -62,6 +62,13 @@
Memory: SVF Memory: SVF
Flash: SVF Flash: SVF
- ID: antmicro_ddr4_tester
Description: Antmicro Data Center DRAM Tester
URL: https://opensource.antmicro.com/projects/data-center-dram-tester
FPGA: Kintex7 xc7k160t
Memory: OK
Flash: OK
- ID: arty_a7_35t - ID: arty_a7_35t
Description: Digilent Arty A7 Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start

1
src/board.hpp
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@ -111,6 +111,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7101", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax7101", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */ /* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),