diff --git a/doc/boards.yml b/doc/boards.yml
index c2a2089..5f9014b 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -62,6 +62,13 @@
   Memory: SVF
   Flash: SVF
 
+- ID: antmicro_ddr4_tester
+  Description: Antmicro Data Center DRAM Tester
+  URL: https://opensource.antmicro.com/projects/data-center-dram-tester
+  FPGA: Kintex7 xc7k160t
+  Memory: OK
+  Flash: OK
+
 - ID: arty_a7_35t
   Description: Digilent Arty A7
   URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
diff --git a/src/board.hpp b/src/board.hpp
index e45bb28..2169580 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -111,6 +111,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("alinx_ax516",     "xc6slx16csg324", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("alinx_ax7101",    "xc7a100tfgg484", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("alinx_ax7102",    "xc7a100tfgg484", "",         0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
 	/* left for backward compatibility, use right name instead */
 	JTAG_BOARD("arty",            "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),
 	JTAG_BOARD("arty_a7_35t",     "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),