adding reference to Tang Nano 4K kit in doc
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@ -47,6 +47,7 @@ openFPGALoader -b arty -f bitstream.bit # Writing in flash (non-volatile)
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| | [Scarab Hardware MiniSpartan6+](https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use) | Spartan6</br>xc6slx25-3-ftg256 | OK | NT |
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| | [Scarab Hardware MiniSpartan6+](https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use) | Spartan6</br>xc6slx25-3-ftg256 | OK | NT |
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| **spartanEdgeAccelBoard** | [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) | Spartan7</br>xc7s15ftgb196 | OK | NA |
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| **spartanEdgeAccelBoard** | [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) | Spartan7</br>xc7s15ftgb196 | OK | NA |
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| **tangnano** | [Sipeed Tang Nano](https://tangnano.sipeed.com/en/) | littleBee</br>GW1N-1 | OK | |
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| **tangnano** | [Sipeed Tang Nano](https://tangnano.sipeed.com/en/) | littleBee</br>GW1N-1 | OK | |
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| **tangnano4k** | [Sipeed Tang Nano 4K](https://tangnano.sipeed.com/en/) | littleBee</br>GW1NSR-4 | OK | |
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| **tec0117** | [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) | littleBee</br>GW1NR-9 | OK | IF |
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| **tec0117** | [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) | littleBee</br>GW1NR-9 | OK | IF |
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| **xtrx** | [FairWaves XTRXPro](https://www.crowdsupply.com/fairwaves/xtrx) | Artix</br>xc7a50tcpg236 | OK | OK |
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| **xtrx** | [FairWaves XTRXPro](https://www.crowdsupply.com/fairwaves/xtrx) | Artix</br>xc7a50tcpg236 | OK | OK |
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| **xyloni_spi** | [Efinix Xyloni](https://www.efinixinc.com/products-devkits-xyloni.html) | Trion</br>T8F81 | NA | AS |
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| **xyloni_spi** | [Efinix Xyloni](https://www.efinixinc.com/products-devkits-xyloni.html) | Trion</br>T8F81 | NA | AS |
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@ -4,7 +4,7 @@
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|--------:|:---------------------------------------------------------------------------------------------------------------------------------|:-------|:------|
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|--------:|:---------------------------------------------------------------------------------------------------------------------------------|:-------|:------|
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| Anlogic | [EG4S20](http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3) | OK | AS |
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| Anlogic | [EG4S20](http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3) | OK | AS |
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| Efinix | [Trion T8](https://www.efinixinc.com/products-trion.html) | NA | OK |
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| Efinix | [Trion T8](https://www.efinixinc.com/products-trion.html) | NA | OK |
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| Gowin | [GW1N (GW1N-1, GW1N-4, GW1NR-9, GW1NS-2C)](https://www.gowinsemi.com/en/product/detail/2/) | OK | IF |
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| Gowin | [GW1N (GW1N-1, GW1N-4, GW1NR-9, GW1NS-2C, GW1NSR-4)](https://www.gowinsemi.com/en/product/detail/2/) | OK | IF |
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| Intel | Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) | OK | OK |
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| Intel | Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) | OK | OK |
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| | Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) | OK | OK |
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| | Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) | OK | OK |
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| | Cyclone V E [5CEA2, 5CEBA4](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html) | OK | OK |
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| | Cyclone V E [5CEA2, 5CEBA4](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html) | OK | OK |
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@ -1,6 +1,6 @@
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# Gowin notes
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# Gowin notes
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## GOWIN GW1N (Trenz TEC0117, Sipeed Tang Nano, Honeycomb and RUNBER)
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## GOWIN GW1N (Trenz TEC0117, Sipeed Tang Nano, Sipeed Tang Nano 4K, Honeycomb and RUNBER)
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*.fs* file is the default format generated by *Gowin IDE*, so nothing
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*.fs* file is the default format generated by *Gowin IDE*, so nothing
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special must be done to generates this file.
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special must be done to generates this file.
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@ -18,6 +18,7 @@ openFPGALoader -m -b BOARD_NAME impl/pnr/*.fs
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where *BOARD_NAME* is:
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where *BOARD_NAME* is:
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- *tec0117*
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- *tec0117*
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- *tangnano*
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- *tangnano*
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- *tangnano4k"
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- *runber*
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- *runber*
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### Flash (only with Trenz TEC0117 and runber):
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### Flash (only with Trenz TEC0117 and runber):
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@ -136,6 +136,7 @@ static std::map <std::string, target_board_t> board_list = {
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JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tangnano", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tangnano", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tangnano4k", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0,
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JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0,
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FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD, CABLE_DEFAULT),
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FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD, CABLE_DEFAULT),
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