153 lines
6.2 KiB
C++
153 lines
6.2 KiB
C++
// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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#ifndef BOARD_HPP
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#define BOARD_HPP
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#include <map>
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#include "cable.hpp"
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/* AN_232R-01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R */
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enum {
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FT232RL_TXD = (1 << 0),
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FT232RL_RXD = (1 << 1),
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FT232RL_RTS = (1 << 2),
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FT232RL_CTS = (1 << 3),
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FT232RL_DTR = (1 << 4),
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FT232RL_DSR = (1 << 5),
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FT232RL_DCD = (1 << 6),
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FT232RL_RI = (1 << 7)
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};
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/* AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes */
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enum {
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DBUS0 = (1 << 0),
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DBUS1 = (1 << 1),
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DBUS2 = (1 << 2),
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DBUS3 = (1 << 3),
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DBUS4 = (1 << 4),
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DBUS5 = (1 << 5),
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DBUS6 = (1 << 6),
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DBUS7 = (1 << 7),
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CBUS0 = (1 << 8),
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CBUS1 = (1 << 9),
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CBUS2 = (1 << 10),
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CBUS3 = (1 << 11),
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CBUS4 = (1 << 12),
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CBUS5 = (1 << 13),
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CBUS6 = (1 << 14),
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CBUS7 = (1 << 15)
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};
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/*!
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* \brief for bitbang mode this structure provide value for each JTAG signals
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*/
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typedef struct {
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uint8_t tms_pin; /*! TMS pin value */
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uint8_t tck_pin; /*! TCK pin value */
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uint8_t tdi_pin; /*! TDI pin value */
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uint8_t tdo_pin; /*! TDO pin value */
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} jtag_pins_conf_t;
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typedef struct {
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uint16_t cs_pin; /*! CS pin value */
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uint16_t sck_pin; /*! SCK pin value */
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uint16_t miso_pin; /*! MISO pin value */
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uint16_t mosi_pin; /*! MOSI pin value */
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uint16_t holdn_pin; /*! HOLDN pin value */
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uint16_t wpn_pin; /*! WPN pin value */
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} spi_pins_conf_t;
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enum {
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COMM_JTAG = (1 << 0),
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COMM_SPI = (1 << 1),
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COMM_DFU = (1 << 2),
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};
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/*!
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* \brief a board has a target cable and optionnally a pin configuration
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* (bitbang mode)
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*/
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typedef struct {
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std::string manufacturer;
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std::string cable_name; /*! provide name of one entry in cable_list */
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std::string fpga_part; /*! provide full fpga model name with package */
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uint16_t reset_pin; /*! reset pin value */
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uint16_t done_pin; /*! done pin value */
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uint16_t mode; /*! communication type (JTAG or SPI) */
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jtag_pins_conf_t jtag_pins_config; /*! for bitbang, provide struct with pins value */
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spi_pins_conf_t spi_pins_config; /*! for SPI, provide struct with pins value */
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uint32_t default_freq; /* Default clock speed: 0 = use cable default */
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uint16_t vid; /* optional VID: used only with DFU */
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uint16_t pid; /* optional VID: used only with DFU */
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} target_board_t;
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#define CABLE_DEFAULT 0
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#define CABLE_MHZ(_m) ((_m) * 1000000)
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#define JTAG_BOARD(_name, _fpga_part, _cable, _rst, _done, _freq) \
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{_name, {"", _cable, _fpga_part, _rst, _done, COMM_JTAG, {}, {}, _freq, 0, 0}}
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#define JTAG_BITBANG_BOARD(_name, _fpga_part, _cable, _rst, _done, _tms, _tck, _tdi, _tdo, _freq) \
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{_name, {"", _cable, _fpga_part, _rst, _done, COMM_JTAG, { _tms, _tck, _tdi, _tdo }, {}, \
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_freq, 0, 0}}
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#define SPI_BOARD(_name, _manufacturer, _cable, _rst, _done, _cs, _sck, _si, _so, _holdn, _wpn, _freq) \
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{_name, {_manufacturer, _cable, "", _rst, _done, COMM_SPI, {}, \
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{_cs, _sck, _so, _si, _holdn, _wpn}, _freq, 0, 0}}
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#define DFU_BOARD(_name, _fpga_part, _cable, _vid, _pid) \
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{_name, {"", _cable, _fpga_part, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid}}
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static std::map <std::string, target_board_t> board_list = {
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JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
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JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("cyc1000", "10cl025256", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0", "", "usb-blaster",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0nano", "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0nanoSoc", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de10nano", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("ecp5_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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SPI_BOARD("fireant", "efinix", "ft232",
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DBUS4, DBUS5, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
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DFU_BOARD("fomu", "", "dfu", 0x1209, 0x5bf0),
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/* most ice40 boards uses the same pinout */
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SPI_BOARD("ice40_generic", "lattice", "ft2232",
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DBUS7, DBUS6,
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DBUS4, DBUS0, DBUS1, DBUS2,
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0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("licheeTang", "", "anlogicCable", 0, 0, CABLE_DEFAULT),
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/* left for backward compatibility, use tec0117 instead */
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JTAG_BOARD("littleBee", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),
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DFU_BOARD("orangeCrab", "", "dfu", 0x1209, 0x5af0),
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JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tangnano", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tangnano4k", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0,
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FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD, CABLE_DEFAULT),
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JTAG_BITBANG_BOARD("ulx3s", "", "ft231X", 0, 0,
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FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT),
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JTAG_BOARD("ecpix5", "", "ecpix5-debug", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("xtrx", "xc7a50tcpg236", "" , 0, 0, CABLE_DEFAULT),
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SPI_BOARD("xyloni_spi", "efinix", "efinix_spi",
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DBUS4 | DBUS7, DBUS5, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
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JTAG_BOARD("zedboard", "xc7z020-clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
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};
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#endif
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