add kintex ultrascale plus family to xilinx.cpp

src/part.hpp

@@ -65,7 +65,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
-	{0x04A62093, {"xilinx", "kintexusp", "xcku5p", 6}},
+	{0x04a62093, {"xilinx", "kintexusp", "xcku5p", 6}},
 
 	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},
 	{0x14b79093, {"xilinx", "virtexusp", "xcvu37p", 18}},

src/xilinx.cpp

@@ -59,6 +59,7 @@ static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
 			"default",
 			{
 				{ "USER1",       {0x02} },
+				{ "USER2",       {0x03} },
 				{ "CFG_IN",      {0x05} },
 				{ "USERCODE",    {0x08} },
 				{ "IDCODE",      {0x09} },
@@ -196,6 +197,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEX_FAMILY;
 	} else if (family == "kintexus") {
 		_fpga_family = KINTEXUS_FAMILY;
+	} else if (family == "kintexusp") {
+		_fpga_family = KINTEXUSP_FAMILY;
 	} else if (family == "virtexusp") {
 		_fpga_family = VIRTEXUSP_FAMILY;
 		_ircode_map = ircode_mapping.at("virtexusp");

src/xilinx.hpp

@@ -160,6 +160,7 @@ class Xilinx: public Device, SPIInterface {
 			ARTIX_FAMILY,
 			KINTEX_FAMILY,
 			KINTEXUS_FAMILY,
+			KINTEXUSP_FAMILY,
 			ZYNQ_FAMILY,
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,