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openFPGALoader
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initial kcu116 support

This commit is contained in:
Maik 2023-03-01 09:29:02 +01:00
parent 567d854edf
commit 46bc735888
8 changed files with 37 additions and 2 deletions
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1
spiOverJtag/Makefile
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@ -8,6 +8,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx
xc7k160tffg676 \
xc7k325tffg676 xc7k325tffg900 \
xc7k420tffg901 \
xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

13
spiOverJtag/build.py
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@ -58,6 +58,9 @@ elif subpart == "xc3s":
elif subpart == "xcvu":
family = "Virtex UltraScale"
tool = "vivado"
elif subpart == "xcku":
family = "Virtex UltraScale"
tool = "vivado"
else:
print("Error: unknown device")
os.sys.exit()
@ -92,6 +95,7 @@ if tool in ["ise", "vivado"]:
"xc7s50csga324" : "xc7s_csga324",
"xcvu9p-flga2104" : "xcvu9p_flga2104",
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
"xcku5p-ffvb676" : "xcku5p_ffvb676",
}[part]
if tool == "ise":
cst_type = "UCF"
@ -127,8 +131,8 @@ if tool in ["ise", "vivado"]:
else:
cst_type = "xdc"
if family == "Virtex UltraScale":
tool_options = {'part': part + '-1-e'}
if part == "xcvu9p-flga2104":
tool_options = {'part': part + '-1-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
@ -136,6 +140,13 @@ if tool in ["ise", "vivado"]:
'default': 1}
elif part == "xcvu37p-fsvh2892":
tool_options = {'part': part + '-2L-e'}
elif part == "xcku5p-ffvb676":
tool_options = {'part': part + '-2-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'secondary flash',
'default': 1}
else:
tool_options = {'part': part + '-1'}
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()

19
spiOverJtag/constr_xcku5p_ffvb676.xdc Normal file
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@ -0,0 +1,19 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# Secondary QSPI flash
set_property PACKAGE_PIN N23 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN P23 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R20 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R21 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN U22 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65

BIN
spiOverJtag/spiOverJtag_xcku5p-ffvb676.bit.gz Normal file
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Binary file not shown.

1
src/board.hpp
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@ -213,6 +213,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("zc706", "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zcu102", "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zcu106", "xczu7evffvc1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kcu116", "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT)

1
src/mcsParser.cpp
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@ -43,6 +43,7 @@ int McsParser::parse()
{
string str;
istringstream lineStream(_raw_data);
_bit_data.resize(_file_size);
while (std::getline(lineStream, str, '\n')) {
char *ptr;

2
src/part.hpp
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@ -65,6 +65,8 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x03727093, {"xilinx", "zynq", "xc7z020", 6}},
{0x23731093, {"xilinx", "zynq", "xc7z045", 6}},
{0x04A62093, {"xilinx", "kintexusp", "xcku5p", 6}},
{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},
{0x14b79093, {"xilinx", "virtexusp", "xcvu37p", 18}},

2
src/xilinx.cpp
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@ -167,7 +167,7 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
_secondary_file_extension = secondary_filename.substr(
secondary_filename.find_last_of(".") + 1);
_mode = Device::SPI_MODE;
if (_device_package != "xcvu9p-flga2104") {
if (!(_device_package == "xcvu9p-flga2104" || _device_package == "xcku5p-ffvb676")) {
throw std::runtime_error("Error: secondary flash unavailable");
}
}