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openFPGALoader
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openFPGALoader/spiOverJtag/Makefile

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spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
XILINX_PARTS := xc6slx45csg324 xc6slx100fgg484 \
xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
xc7a50tcpg236 xc7a75tfgg484 xc7a100tfgg484 xc7a200tsbg484 \
xc7s50csga324
XILINX_BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
ALTERA_PARTS := 10cl025256 ep4ce2217 5ce223
ALTERA_BIT_FILES := $(addsuffix .rbf, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)
add design and bitstream to access SPI through JTAG
2019-10-05 19:03:28 +02:00
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
all: $(BIT_FILES)
spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
$(XILINX_BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.bit
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
cp $< $@
spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
./build.py $*
$(ALTERA_BIT_FILES): spiOverJtag_%.rbf: tmp_%/spiOverJtag.sof
quartus_cpf --option=bitstream_compression=off -c $< $@
tmp_%/spiOverJtag.sof: altera_spiOverJtag.v
./build.py $*
add design and bitstream to access SPI through JTAG
2019-10-05 19:03:28 +02:00
clean:
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
-rm -rf tmp_* *.jou *.log .Xil