openFPGALoader/spiOverJtag/Makefile

VIVADO := vivado -nolog -nojournal -mode batch -source
PARTS := xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a50tcpg236 xc7a75tfgg484 xc7a100tfgg484 xc7a200tsbg484 xc7s50csga324
BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(PARTS)))

all: $(BIT_FILES)

$(BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit
	cp $< $@
tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit : xilinx_spiOverJtag.vhd
	$(VIVADO) xilinx_spiOverJtag.tcl -tclargs $*

clean:
	-rm -rf tmp_* *.jou *.log .Xil
add design and bitstream to access SPI through JTAG 2019-10-05 19:03:28 +02:00			`VIVADO := vivado -nolog -nojournal -mode batch -source`
add basys3 support 2021-04-20 21:28:14 +02:00			`PARTS := xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a50tcpg236 xc7a75tfgg484 xc7a100tfgg484 xc7a200tsbg484 xc7s50csga324`
rework xilinx fpga spiOverJtag to respect model/package 2021-04-19 21:17:08 +02:00			`BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(PARTS)))`
add design and bitstream to access SPI through JTAG 2019-10-05 19:03:28 +02:00
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings. 2020-08-08 11:42:38 +02:00			`all: $(BIT_FILES)`

			`$(BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit`
			`cp $< $@`
rework xilinx fpga spiOverJtag to respect model/package 2021-04-19 21:17:08 +02:00			`tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit : xilinx_spiOverJtag.vhd`
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings. 2020-08-08 11:42:38 +02:00			`$(VIVADO) xilinx_spiOverJtag.tcl -tclargs $*`
add design and bitstream to access SPI through JTAG 2019-10-05 19:03:28 +02:00
			`clean:`
Support Arty S7-50 Added Xilinx xc7s50 device to part.hpp; added support for generating spiOverJtag bitstream file for that device and added bitstream to repo. Converted xdc file from DOC line endings to native line endings. 2020-08-08 11:42:38 +02:00			`-rm -rf tmp_* .jou .log .Xil`