Holger Vogt 65fc0ad8a6 Add analog code model astate. ...

It reports the previous state (delayed by 1 to 3 time steps)
of the input node. Single or differential voltage or current.

2026-02-03 13:57:57 +01:00

..

d_lut

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

d_process

Fix d_process named pipes example. Use the correct gtkwave command for MacOS.

2025-05-24 11:03:52 +02:00

d_source

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

delay

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

delta-sigma

add y-axis label

2022-02-01 12:21:08 +01:00

filesource

Add missing value in the last line.

2025-08-28 12:14:50 +02:00

ghdl

Add co-simulation with VHDL, using the GHDL compiler and d_cosim.

2025-05-24 11:05:33 +02:00

icarus_verilog

Fix ordering of parameter definition and use.

2025-05-24 11:00:18 +02:00

original-examples

Add null-pointer checks to some code that crashed when trying

2023-11-09 12:07:31 +00:00

pll

Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,

2025-05-24 11:28:42 +02:00

pwm-osc

Examples for d_pwm and d_osc

2022-12-11 15:27:42 +01:00

see

Tiny modifications of SEE examples

2025-07-29 10:47:32 +02:00

state

Fix d_process named pipes example. Use the correct gtkwave command for MacOS.

2025-05-24 11:03:52 +02:00

table

New tables for MOS devices

2022-10-07 13:11:18 +02:00

transmission_lines

Fix the xspice transmission_line examples.

2025-07-29 10:57:55 +02:00

various

Add analog code model astate.

2026-02-03 13:57:57 +01:00

verilator

Fix ordering of parameter definition and use.

2025-05-24 11:00:18 +02:00