Holger Vogt 882acb73fd Add a monitoring output the the seegen instance		2025-06-08 10:09:28 +02:00
..
d_lut	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
d_process	Fix d_process named pipes example. Use the correct gtkwave command for MacOS.	2025-01-26 22:57:20 +01:00
d_source	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delay	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delta-sigma	add y-axis label	2022-02-01 12:21:08 +01:00
filesource	Example for sending a text string over the subcircuit boundary.	2024-12-06 22:48:31 +01:00
ghdl	Add co-simulation with VHDL, using the GHDL compiler and d_cosim.	2025-01-30 09:45:35 +00:00
icarus_verilog	Fix ordering of parameter definition and use.	2025-01-20 09:28:09 +01:00
original-examples	Add null-pointer checks to some code that crashed when trying	2023-11-09 12:07:31 +00:00
pll	Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,	2025-04-12 18:20:20 +02:00
pwm-osc	Examples for d_pwm and d_osc	2022-12-11 15:27:42 +01:00
see	Add a monitoring output the the seegen instance	2025-06-08 10:09:28 +02:00
state	Fix d_process named pipes example. Use the correct gtkwave command for MacOS.	2025-01-26 22:57:20 +01:00
table	New tables for MOS devices	2022-10-07 13:11:18 +02:00
various	Various filter examples using Laplace expression x_fer	2023-01-20 15:07:37 +01:00
verilator	Fix ordering of parameter definition and use.	2025-01-20 09:28:09 +01:00