Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,

behaviour as before.  Add similar pll-digital-iplot.cir as a
demonstration of iplot with analogue and digital nodes.
This commit is contained in:
Giles Atkinson 2025-03-31 10:33:49 +01:00 committed by Holger Vogt
parent a91cd8292c
commit 78581e3ad4
3 changed files with 37 additions and 13 deletions

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@ -0,0 +1,20 @@
* pll circuit using xspice code models: version with iplot including
* digital nodes.
.include shared-pll-xspice.cir
* An additional node to scale the analog signal.
bdisplay controlX4 0 v=v(cont)*4
.control
save cont controlX4 s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
iplot -o controlx4 d_d+4.5 d_u
tran 0.1n $&simtime uic
rusage
plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
*plot cont
.endc
.end

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@ -0,0 +1,15 @@
* pll circuit using xspice code models: version with analog-only iplot
* output frequency 400 MHz
* locked to a 1 or 10 MHz reference
.include shared-pll-xspice.cir
.control
save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
iplot -d 4000 cont
tran 0.1n $&simtime uic
rusage
plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
.endc
.end

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@ -1,4 +1,5 @@
* pll circuit using xspice code models
* pll circuit using xspice code models: shared by pll_xspice.cir and
* pll_digital_iplot.cir
* output frequency 400 MHz
* locked to a 1 or 10 MHz reference
@ -62,16 +63,6 @@ abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un
+ input_load = 5.0e-12 t_rise = 1e-10
+ t_fall = 1e-10)
.control
save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
iplot -d 4000 cont
tran 0.1n $&simtime uic
rusage
plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
*plot cont
.endc
*model = bsim3v3
*Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
@ -140,5 +131,3 @@ plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
+Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0
+Kt1l=0
.end