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Monte_Carlo
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Fix internet address
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2022-04-25 21:30:07 +02:00 |
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TransImpedanceAmp
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…
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TransmissionLines
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Better visibility of the results
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2023-07-15 11:11:48 +02:00 |
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cider
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When Cider models are present, a normal batch mode sp_shutdown (for example, ngspice -b cmosinv.cir) will call com_quit(NULL). This cleans up so that valgrind will find no leaks in Cider devices after sp_shutdown. To disable this feature, set the environment variable CIDER_COM_QUIT="OFF". Even though it really does not matter that Cider memory is cleared just before exit, it makes it cleaner for valgrind checks.
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2023-07-15 11:32:37 +02:00 |
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control_structs
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S-parameters: Replace S11 by S_1_1 etc. to avoid ambiguity
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2022-04-29 07:29:14 +02:00 |
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ddt
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Remove unused variable debarr.
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2022-12-11 15:39:10 +01:00 |
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digital
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Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE.
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2023-07-31 14:27:59 +02:00 |
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hicum2
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…
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inductive-systems
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…
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klu/Circuits
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Added missing ISCAS85 libraries
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2023-08-16 11:14:18 +02:00 |
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loops
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Repeat loop requires plain number, transformed vector, or transformed variable
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2024-03-19 17:05:10 +01:00 |
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measure
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measure example with expression evaluation
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2024-03-29 17:12:40 +01:00 |
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memristor
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Obtain memory and simulation time
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2022-01-03 22:11:15 +01:00 |
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mos
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File encoding is now UTF-8
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2024-11-02 22:22:22 +01:00 |
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noise
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implement osdi noise support
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2023-11-04 19:36:30 +01:00 |
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numparam
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Try to clarify the mechanism of parameter substitution and add
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2024-11-02 22:41:59 +01:00 |
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optran
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special ngbehavior needed
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2023-01-09 16:31:01 +01:00 |
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osdi
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add examples for OSDI noise
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2023-11-04 19:36:30 +01:00 |
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p-to-n-examples
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Use sparse, as KLU will fail.
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2023-09-10 13:43:09 +02:00 |
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paranoia
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Fix some typos.
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2023-12-18 20:13:06 +01:00 |
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plot
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…
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probe
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Enable power measurement for W switch
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2022-10-07 13:18:51 +02:00 |
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proc2mod
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…
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pss
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…
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snapshot
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…
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soa
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Add a comment to say that LT/PSPICE compatability is needed.
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2023-07-31 14:29:50 +02:00 |
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soi
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…
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sp
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better visibility
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2023-07-31 14:30:37 +02:00 |
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svg
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File encoding is now UTF-8
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2024-11-02 22:22:22 +01:00 |
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tclspice
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…
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transient-noise
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…
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utf-8/стекло
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…
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various
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Add a transformer with parameters on the .subckt line
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2024-01-24 10:11:44 +01:00 |
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vbic
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vbic: rm obsolete regression test
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2024-05-01 10:34:01 +02:00 |
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vdmos
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Add vto model parameter (the default has changed!), add .ic
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2023-05-27 10:47:43 +02:00 |
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xspice
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Add additional examples of Verilog co-simulation and share the Verilog
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2024-11-02 22:30:32 +01:00 |
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