539 lines
14 KiB
Plaintext
539 lines
14 KiB
Plaintext
DEVICES
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---------------------------------------------------------------------------
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This file contains the status of devices available in ngspice. This file
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will be updated every time the device pecific code is altered or changed.
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This file it is useful in writing ngspice documentation.
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***************************************************************************
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************************* Linear devices ********************************
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***************************************************************************
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CAP - Capacitor
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Initial Release.
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Ver: N/A
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Class: C
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Level: 1 (and only)
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Status:
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Enhancements over the original model:
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- Parallel Multiplier
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- Temperature difference from circuit temperature
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- Preliminary technology scaling support
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- Model capacitance
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- Cj calculation based on relative dielectric constant
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and insulator thickness
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IND - Inductor
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Initial Release.
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Ver: N/A
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Class: L
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Level: 1 (and only)
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Status:
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Enhancements over the original model:
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- Parallel Multiplier
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- Temperature difference from circuit temperature
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- Preliminary technology scaling support
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- Model inductance
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- Inductance calculation for toroids or solenoids
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on the model line.
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RES - Simple linear resistor
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Initial Release.
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Ver: N/A
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Class: R
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Level: 1 (and only)
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Status:
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Enhancements over the original model:
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- Parallel Multiplier
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- Different value for ac analysis
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- Temperature difference from circuit temperature
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- Noiseless resistor
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- Flicker noise
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- Preliminary technology scaling support
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***************************************************************************
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********************* Distributed elements ********************************
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***************************************************************************
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TRA - Transmission line
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Initial release
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LTRA - Lossy Transmission line
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Initial release
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URC - Uniform distributed RC line
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Initial release
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***************************************************************************
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**************************** V/I Sources *****************************
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***************************************************************************
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ASRC - Arbitrary Source
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Initial Release
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CCCS - Current Controlled Current Source
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Initial Release
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CCVS - Current Controlled Voltage Source
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Initial Release
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ISRC - Independent Current Source
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Initial Release
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VCCS - Voltage Controlled Current Source
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Initial Release
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VCVS - Voltage Controlled Voltage Source
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Initial Release
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VSRC - Independent Voltage Source
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Initial Release
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***************************************************************************
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**************************** Switches ****************************
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***************************************************************************
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CSW - Current controlled switch
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Initial release
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SW - Voltage controlled switch
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Initial release
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***************************************************************************
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**************************** Diodes ****************************
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***************************************************************************
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DIO - Junction Diode
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Initial Release.
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Ver: N/A
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Class: D
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Level: 1 (and only)
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Status:
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Enhancements over the original model:
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- Parallel Multiplier
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- Temperature difference from circuit temperature
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- Forward and reverse knee currents
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- Periphery (sidewall) effects
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- Temperature correction of some parameters
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***************************************************************************
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************************* Bipolar Devices *************************
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***************************************************************************
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BJT - Bipolar Junction Transistor
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Initial Release.
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Ver: N/A
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Class: Q
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Level: 1
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Status:
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Enhancements over the original model:
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- Parallel Multiplier
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- Temperature difference from circuit temperature
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- Different area parameters for collector, base and emitter
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BJT2 - Bipolar Junction Trasistor
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Initial Release.
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Ver: N/A
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Class: Q
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Level: 2
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Status:
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This is the BJT model written by Alan Gillespie to support lateral
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devices. The model has been hacked by Dietmar Warning fixing some bugs
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and adding some features (temp. correction on resistors).
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Enhancements over the original model:
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- Temperature correction on rc,rb,re
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- Parallel Multiplier
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- Temperature difference from circuit temperature
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- Different area parameters for collector, base and emitter
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***************************************************************************
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***************************** FET Devices ***************************
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***************************************************************************
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JFET - Junction Field Effect transistor
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Initial Release.
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Ver: N/A
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Class: J
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Level: 1
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Status:
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This is the original spice JFET model.
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Enhancements over the original model:
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- Alan Gillespie's modified diode model
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- Parallel multiplier
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- Instance temperature as difference for circuit temperature
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JFET2 - Junction Field Effect Transistor (PS model)
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Initial Release.
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Ver: N/A
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Class: J
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Level: 2
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Status:
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This is the Parker Skellern model.
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Web Site:
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http://www.elec.mq.edu.au/cnerf/models/psmodel/
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Enhancements over the original model:
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- Parallel multiplier
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- Instance temperature as difference for circuit temperature
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***************************************************************************
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*************************** HFET devices ***************************
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***************************************************************************
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HFET - HFET Level 1 (MacSpice3f4)
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Initial Release.
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Ver: N/A
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Class: Z
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Level: 5
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Instance temperature as difference for circuit temperature
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- Added pole-zero analysis
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HFET2 - HFET Level 2 (MacSpice3f4)
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Initial Release.
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Ver: N/A
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Class: Z
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Level: 6
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Instance temperature as difference for circuit temperature
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- Added pole-zero analysis
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***************************************************************************
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*************************** MES devices ***************************
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***************************************************************************
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MES - MESfet model
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Initial Release.
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Ver: N/A
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Class: Z
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Level: 1
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Alan Gillespie junction diodes implementation
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MESA - MESA model (MacSpice3f4)
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Initial Release.
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Ver: N/A
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Class: Z
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Level: 2,3,4
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Status:
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This is a multilevel model. It contains code for mesa levels
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2,3 and 4
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Enhancements over the original model:
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- Parallel multiplier
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- Instance temperature as difference from circuit temperature
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- Added pole-zero analysis
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***************************************************************************
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**************************** MOS devices ****************************
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***************************************************************************
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MOS1 - Level 1 MOS model
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Initial Release.
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Ver: N/A
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Class: M
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Level: 1
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Status:
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This is the so-called Schichman-Hodges model.
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Enhancements over the original model:
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- Parallel multiplier
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- Temperature difference from circuit temperature
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MOS2 - Level 2 MOS model
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Initial Release.
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Ver: N/A
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Class: M
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Level: 2
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Status:
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This is the so-called Grove-Frohman model.
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Enhancements over the original model:
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- Parallel multiplier
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- Temperature difference from circuit temperature
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MOS3 - Level 3 MOS model
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Initial Release.
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Ver: N/A
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Class: M
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Level: 3
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Temperature difference from circuit temperature
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MOS6 - Level 6 MOS model
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Initial Release.
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Ver: N/A
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Class: M
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Level: 6
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Temperature difference from circuit temperature
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MOS9 - Level 9 MOS model
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Initial Release.
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Ver: N/A
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Class: M
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Level: 9
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Status:
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Enhancements over the original model:
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- Temperature difference from circuit temperature
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BSIM1 - BSIM model level 1
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Initial Release.
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Ver: N/A
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Class: M
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Level: 4
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Noise analysis
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BUGS:
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Distortion analysis probably does not
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work with "parallel" devices. Equations
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are too intricate to deal with. Any one
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has ideas on the subject ?
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BSIM2 - BSIM model level 2
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Initial Release.
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Ver: N/A
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Class: M
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Level: 5
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Status:
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Enhancements over the original model:
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- Parallel multiplier
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- Noise analysis
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BSIM3 - BSIM model level 3
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Initial Release.
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Ver: 3.2.4
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Class: M
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Level: 8
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Status: TO BE TESTED
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This is the BSIM3v3.2.4 model from Berkeley device group.
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You can find some test netlists with results for this model
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on its web site.
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Web site:
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http://www-device.eecs.berkeley.edu/~bsim3
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Enhancements over the original model:
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- Parallel Multiplier
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- ACM Area Calculation Method
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- Multirevision code (supports all 3v3.2 minor revisions)
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- NodesetFix
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BSIM3v1 - BSIM model level 3
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Initial Release.
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Ver: N/A
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Class: M
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Level: 49
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Status: TO BE TESTED AND IMPROVED
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This is the BSIM3v3.1 model modified by Serban Popescu.
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This is level 49 model. It is an implementation that supports
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"HDIF" and "M" parameters.
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BSIM3v2 - BSIM model level 3
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Initial Relese.
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Ver: 3.2
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Class: M
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Level: 50
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Status: TO BE TESTED
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This is the BSIM3v3.2 model. It is included only for compatibility
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with existing netlists and parameters files. As always, tests
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are availabe on the Berkeley's device group site.
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Web site:
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http://www-device.eecs.berkeley.edu/~bsim3
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BSIM4 - BSIM model level 4 (0.18 um)
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Initial Release.
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Ver: 4.2.1 (Updated in rework 14)
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Class: M
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Level: 14
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Status: TO BE TESTED
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This is the BSIM4 device model from Berkeley Device Group.
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Test are available on its web site.
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Web site:
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http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
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*) Rework 14: Updated to 4.21 YET UNTESTED.
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HiSIM - Hiroshima-university STARC IGFET Model
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Initial Release.
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Ver: 1.2.0
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Class: M
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Level: TBD
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Status: TO BE TESTED
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This is the HiSIM model available from Hiroshima University
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(Ultra-Small Device Engineering Laboratory)
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Web site:
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http://home.hiroshima-u.ac.jp/usdl/HiSIM.shtml
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http://www.starc.or.jp/kaihatu/pdgr/hisim/index.html
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Enhancements over the original model:
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- Parallel Multiplier
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- NodesetFix
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***************************************************************************
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***************************** SOI Devices ****************************
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***************************************************************************
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BSIM3SOI_FD - SOI model (fully depleted devices)
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Initial Release.
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Ver: 2.1.
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Class: M
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Level: 11
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Status: TO BE TESTED.
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FD model has been integrated.
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There is a bsim3soifd directory under the test
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hierarchy. Test circuits come from the bsim3soi
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Web site at:
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http://www-device.eecs.berkeley.edu/~bsimsoi
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*) rework-14: removed #ifndef NEWCONV code.
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BSIM3SOI_PD - SOI model (partially depleted devices)
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Initial Release.
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Ver: 2.2.1
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Class: M
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Level: 10
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Status: TO BE TESTED.
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PD model has been integrated.
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There is a bsim3soipd directory under the test
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hierarchy. Test circuits come from the bsim3soi
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Web site at:
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http://www-device.eecs.berkeley.edu/~bsimsoi
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*) rework-14: removed #ifndef NEWCONV code.
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BSIM3SOI_DD - SOI Model (dynamic depletion model)
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Initial Release.
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Ver: 2.1
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Class: M
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Level: 12
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Status: TO BE TESTED.
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There is a bsim3soidd directory under the
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test hierarchy. Test circuits come from bsim3soi
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Web site at:
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http://www-device.eecs.berkeley.edu/~bsimsoi
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*) rework-14: removed #ifndef NEWCONV code.
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SOI3 - STAG SOI3 Model
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Initial Release.
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Ver: 2.6
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Class: M
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Level: 62
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Status: TO BE TESTED
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Web site at:
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http://www.micro.ecs.soton.ac.uk/stag/
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***************************************************************************
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**************** Other devices not released as source code ****************
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***************************************************************************
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EKV - EKV model
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Initial Release.
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Ver: 2.6
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Class: M
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Level: 44
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Status: TO BE TESTED
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Note: This model is not released in source code.
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You have to obtain the source code from the address below.
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Web site at:
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http://legwww.epfl.ch/ekv/
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