Holger Vogt 49674ad93e better visibility of standard plot

2026-08-03 17:06:26 +02:00

..

d_lut

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

d_process

Fix d_process named pipes example. Use the correct gtkwave command for MacOS.

2025-05-24 11:03:52 +02:00

d_source

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

delay

Obtain memory and simulation time

2022-01-03 22:11:15 +01:00

delta-sigma

add y-axis label

2022-02-01 12:21:08 +01:00

filesource

better visibility of standard plot

2026-08-03 17:06:26 +02:00

ghdl

Correct three comments.

2026-07-08 22:46:54 +02:00

icarus_verilog

Fix ordering of parameter definition and use.

2025-05-24 11:00:18 +02:00

noise

gain cell as an example for the declarative small signal noise approach

2026-05-24 09:58:53 +02:00

original-examples

Add null-pointer checks to some code that crashed when trying

2023-11-09 12:07:31 +00:00

pll

Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,

2025-05-24 11:28:42 +02:00

pwm-osc

Examples for d_pwm and d_osc

2022-12-11 15:27:42 +01:00

see

Add non-nqs PSP model as well.

2026-04-30 11:22:08 +02:00

state

Add internal plotting via command

2026-04-29 13:03:12 +02:00

table

New tables for MOS devices

2022-10-07 13:11:18 +02:00

transmission_lines

Fix the xspice transmission_line examples.

2025-07-29 10:57:55 +02:00

various

A digital NAND gate 9-stage ring oscillator (less than 30ms simulation time)

2026-07-08 22:42:44 +02:00

verilator

Fix ordering of parameter definition and use.

2025-05-24 11:00:18 +02:00