Holger Vogt 1be27f6ad0 Using mtimeavg		2026-01-20 15:30:28 +01:00
..
Monte_Carlo	…
SkywaterOpenSourcePDK	…
TransImpedanceAmp	…
TransmissionLines	…
cider	Enable CIDER with KLU for DC, OP, and TRAN analyses. Small signal AC analysis is not yet supported for CIDER complex valued device KLU matrices. The examples/cider testcases produce printed simulation result values which have slight differences between Sparse and KLU. Differences are probably expected and in a few cases are ~1-2%, sometimes a little more. This should be good enough for most CIDER analyses. Francesco did a good piece of work. Runtimes are significantly shorter with KLU.	2025-09-08 23:33:41 +02:00
control_structs	…
ddt	…
digital	…
hicum2	…
inductive-systems	…
klu/Circuits	…
loops	…
measure	Enable expressions in a meas statement within a .control section, like	2025-07-29 10:37:59 +02:00
memristor	Better graphics	2026-01-13 15:50:03 +01:00
mos	Update: add frequency measurement and temperature dependency.	2025-11-18 16:01:19 +01:00
noise	…
numparam	…
optran	F5 example removed, obsolete or needs to be improved.	2026-01-02 15:27:39 +01:00
osdi	…
p-to-n-examples	…
paranoia	…
plot	…
probe	Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch.	2026-01-02 20:28:45 +01:00
proc2mod	…
pss	…
shared	…
snapshot	…
soa	Add a comment to say that LT/PSPICE compatability is needed.	2023-07-31 14:29:50 +02:00
soi	enable simulation with 'option newtrunc'	2026-01-07 20:12:35 +01:00
sp	…
svg	…
tclspice	…
transient-noise	Update test description	2025-12-19 12:55:35 +01:00
utf-8/стекло	…
various	Using mtimeavg	2026-01-20 15:30:28 +01:00
vbic	…
vdmos	Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch.	2026-01-02 20:28:45 +01:00
xspice	Add analog code model astate.	2025-09-21 15:52:51 +02:00