Commit Graph

8924 Commits

Author SHA1 Message Date
Holger Vogt 86951501a7 Add eprvcd to the commands which set node names to lower case,
but not the file names after >
Does not work for manually entered eprvcd commands, where the user
has to provide lower case node names.
2023-03-19 15:24:27 +01:00
Giles Atkinson d3ce882ce7 Add inertial delay to missed d_xnor and tidy blank lines in d_xor. 2023-03-19 14:36:19 +01:00
Giles Atkinson f91b5d6637 Inertial delay for remaining simple gates and buffers:
nand or xor open_c open_e, but not tristate.
2023-03-19 14:36:14 +01:00
Giles Atkinson 393be43887 Correct timing of transitions to UNKNOWN. 2023-03-19 14:36:09 +01:00
Giles Atkinson a1e42bd041 Add missed file inertial.h. 2023-03-19 14:36:04 +01:00
Giles Atkinson 6afdc33b21 Interim version of inertial delay for tristate buffer.
This does not handle three-way or mixed transitions.
2023-03-19 14:36:00 +01:00
Giles Atkinson 22f3690fa4 First group of digital code models with improved implementation
of inertial delay: buffer, inverter, and, nor.  Also adds
utility function cm_is_inertial(().
2023-03-19 14:35:56 +01:00
Giles Atkinson a9270aa312 New code-model library functions cm_schedule_output() and cm_getvar().
To be used in the inertial delay code for digital code models.
2023-03-19 14:35:52 +01:00
Giles Atkinson 4d8e17487b Change output event setup in evtload.c so that, when making an event call
to a code model, there is no longer a reference to the value of the event
at the head of the free list.  That allows all such free lists (with the
same data type) to be combined, probably improving performance.
This is in preparation for full implementation of inertial delay for
digital nodes.
2023-03-19 14:35:42 +01:00
Giles Atkinson b09c46d2a5 Allow string-valued parameters to XSPICE device models with no default.
The code model then sees the value NULL.  Needed for the "family"
parameter on logic models, used by automatic bridge insertion.
2023-03-19 14:35:32 +01:00
Brian Taylor 72c8bc45f2 The logicexp example in the PSpice ref. manual has a name with a '+' character (LCN+4). Update lexer_scan. 2023-03-19 14:33:49 +01:00
Brian Taylor 2ac72c62f8 Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays. 2023-03-19 14:33:00 +01:00
Brian Taylor 3ac7d21d15 The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE. 2023-03-19 14:32:54 +01:00
Brian Taylor e041aa2c38 Undo the temporary changes to ifspec.ifs files made by commit abe26ac1fe. 2023-03-19 14:32:48 +01:00
Brian Taylor 2ee1444dfa Temporary changes to add an inertial_delay parameter table. There are no changes to the cfunc.mod files. Thus the additions are ignored. This will prevent MIF unrecognized parameter warnings. 2023-03-19 14:32:24 +01:00
Holger Vogt 36943f4d88 Add eprvcd to the commands which set node names to lower case,
but not the file names after >
Does not work for manually entered eprvcd commands, where the user
has to provide lower case node names.
2023-03-19 12:10:52 +01:00
Holger Vogt 6213145c94 .control section: atanh examples 2023-03-18 22:32:34 +01:00
Holger Vogt 3632a6b4ae We need to translate from degree to rad 2023-03-18 22:32:25 +01:00
Holger Vogt 2a6052517b Fix prvious commit: allow access to all vector elements of cc 2023-03-18 22:32:19 +01:00
Holger Vogt 68156fa62c Complex number handling other than MSVC 2023-03-18 22:32:07 +01:00
Holger Vogt 71571a1432 Add function atanh to .control section 2023-03-18 22:31:48 +01:00
Holger Vogt 3996d27b29 Make code a little more efficient 2023-03-18 22:31:33 +01:00
Holger Vogt 7af6c4a661 Re-enable single line parameter lists, separated by commas 2023-03-18 22:31:27 +01:00
dwarning f34ff7e63c Revert "implement typedpnjlim as optional limiter for verilog-a models"
This reverts commit f73d3b20a0.
2023-03-18 22:31:04 +01:00
Holger Vogt 7bf550f637 Make code a little more efficient 2023-03-18 22:28:32 +01:00
Holger Vogt 26404d985f .control section: atanh examples 2023-03-18 14:49:11 +01:00
Holger Vogt a5490cc037 We need to translate from degree to rad 2023-03-18 14:42:55 +01:00
Holger Vogt 746121543f Fix prvious commit: allow access to all vector elements of cc 2023-03-18 14:42:51 +01:00
Holger Vogt 33becb211f Complex number handling other than MSVC 2023-03-18 14:42:46 +01:00
Holger Vogt 56639e338d Add function atanh to .control section 2023-03-18 14:42:42 +01:00
Holger Vogt 63d86f5af8 Prevent a crash in strchr
Reported by KiCad Sentry
2023-03-18 14:37:59 +01:00
Holger Vogt e4202ea181 The tc for R, L, C may include an expression
like tc={expression} or tc={expression}, 1.3u or
tc={expression}, {expression2}
2023-03-18 14:37:53 +01:00
Holger Vogt d8505f0069 Make error message more verbose by a hint to the line (fragment). 2023-03-18 14:37:47 +01:00
R. Timothy Edwards c12296182c The code in src/frontend/subckt.c has a fixed-size structure called table at the top with a size set to N_GLOBAL_NODES = 1005. If the number of items passed in formal and actual exceeds 1005, then ngspice exits immediately with an error.
This patch lets table be reallocated on the fly as needed to accommodate the number of subcircuit arguments, instead of being a fixed value.
2023-03-18 14:37:40 +01:00
Holger Vogt e4601c16ee Not a warning but an error, stopping the simulation 2023-03-18 14:37:33 +01:00
Holger Vogt f32f3ac8cd Improve previous commit: A bad .model line leads to a breakup
of the simulation.
2023-03-18 14:37:26 +01:00
Holger Vogt c61acefef7 Prevent crash when a bad .model line is given, like
.model
.model xxx
2023-03-18 14:37:19 +01:00
Holger Vogt 247562c096 Update copyright notice 2023-03-18 14:37:08 +01:00
Holger Vogt bcec3cb5e3 Updating links to ngspice web pages 2023-03-18 14:37:02 +01:00
Holger Vogt 4cc63494db Improve error message
Typo
2023-03-18 14:36:55 +01:00
Brian Taylor 4111aaf110 When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer. 2023-03-18 14:36:45 +01:00
Brian Taylor a6b2773c90 For a ugate timing model, when tphlXX/tplhXX is not found, set the fall/rise delay to zero (1.0e-12). 2023-03-18 14:36:35 +01:00
Brian Taylor 0e5a5a62ac 74F550 and 74F551 have only fall delays on the inverters. Use the fall delay for both rise and fall. 2023-03-18 14:36:23 +01:00
Brian Taylor 3a76a1ef52 Prepare for inertial_delay model parameter. 2023-03-18 14:36:17 +01:00
Brian Taylor 4b30113f60 Check current_subckt is set when printing TRANS_OUT. 2023-03-18 14:36:00 +01:00
Giles Atkinson ae6375c519 Prevent a crash when "portnum" is used in a voltage source without "z0". 2023-03-18 14:35:51 +01:00
Holger Vogt 8915d42241 Prevent crash during .probe p(...) when no subcircuits are given. 2023-03-18 14:35:33 +01:00
Holger Vogt 5ee7a0ad2d prevent crash when defect .model line is given
(no model name or no model type)
2023-03-18 14:35:11 +01:00
Holger Vogt d2fb3fb16b Prevent memory leak.
Remove use controls.
Safeguard against NULL.
2023-03-18 14:34:57 +01:00
Giles Atkinson 79fcb5d4bd Fix plotting bug reported by Robert Turnbull: ngspice-devel 2023-02-10. 2023-03-18 14:34:50 +01:00