Don't call fcn get_adevice_model_name().
Return a fixed value (5) for number of nodes:
This is wrong. It has to be replaced by a safe
method to figure out the number of terminals for
varying Verilog-A device models.
This initial prototype is capable of performing DC, transient and AC
analysis. Not all features of OSDI are supported yet and there are still
some open questions regarding ngspice integration. However many usecase
already work very well and a large amount of CMC models are supported.
The biggest missing feature right now is noise analysis.
test: test case for diode DC working with SH
test: add transient analysis to osdi_diode test
test: added docu text to osdi_diode test
test: added test case directories
fix: bug in osdi_load
test: small change to netlist
fix: implement DEVunsetup
fix: correct behaviour for MODEINITSMSIG
test: osdi diode enable all analysis modes
removed netlist
ignoring test results
added the build of the diode shared object to the python test script
deleting old stuff and always rebuilding the shared object
added diode_va.c to the repo
preparing CI
Create .gitlab-ci.yml file
(testing) add res, cap and multiple devices test
feat: use osdi command to load files
Previously OSDI shared object files were loaded from fixed directories.
This was unreliable, inconvenient and caused conflicts with XSPICE.
This commit remove the old loading mechanism and instead introduces the
`osdi` command that can load (a list of) osdi object files (like the
codemodel command for XSPICE). A typical usecase will use this as a
precommand in the netlist:
.control
pre_osdi foo.osdi
.endc
If the specified file is a relative path it is first resolved relative
to the parent directory of the netlist. If the osdi command is invoked
from the interactive prompt the file is resolved relative to the current
working directory instead.
This commit also moves osdi from the devices folder to the root src
folder like xspice. This better reflects the role of the code as users
may otherthwise (mistakenly) assume that osdi is just another
handwritten model.
test: update tests to new command
fix: do not ignore first parameter
feat: implement log message callback
fix: don't generate ddt matrix/rhs in DC sweep
fix: missing linker script
update to osdi 0.3
(testing) simplify test cases, fix bug
(testing) multiple devices test improvement
(testig) node collapsing bugfix
test: increase tolerance in tests
feat: update to newest OSDI header
fix: temperature update dt behaviour
fix: ignored models
fix: compilation script
fix: allow hicum/l2 to compile with older c++ compilers
fix: set required compiler flags for osdi
fix: disable x by default
fix: add missing SPICE functions
fix: update diode to latest ngspice version
feat: implement python CMC test runner
doc: Add README_OSDI.md
fix: make testing script work with python version before 3.9
fix: free of undefined local variable
fix: do not calculate time derivative during tran op
update osdi version
fixes for compilation on windows
by changing the way "ngspice -a" (autorun option) works. The inserted code
now checks whether a simulation has already run by examining $curplot
before forcing "run". Also at most one simulation is forced to run.
Remove only mfg=something, icrating=, vceo=, type=,
not any combination of text like net_type=... .
Restrict this removal to compatibility modes ps or lt.
in inpc_probe.c.
Make function insert_new_line() non-static
Enable detecting the number of nodes in x-lines
(calls to subciruits) in function get_number_terminals()
Parsing takes default values into account, when
parameter is missing.
S vswitch --> pswitch code model
S_ST vswitch (with hysreresis) --> SW switch
S iswitch --> aswitch code model
S_ST iswitch (with hysreresis) --> CSW switch
Use string handling for replacements: allow parameter
equations in .model lines.
Rewrite is_a_modelname(), when LT is set: only check element lines
beginning with r and c for RKM notation of a number.
So don't use a RKM number (e.g. 4k7) for naming a resistor model.
Holger Vogt
Pascal Kuthe
Giles Atkinson
Brian Taylor