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11,110 Commits 172 Branches 63 Tags 54 MiB
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11110 Commits

Author SHA1 Message Date
Holger Vogt c2f9f6d3f4 retain type=0, type=1, type=+1, or type=-1 in a .model card, 
even if compatmode PS or LT are set.
 2025-07-29 10:52:54 +02:00
dwarning 6aba1f302b allow showmod command for verilog-a models - feature request #100 2025-07-29 10:52:14 +02:00
Árpád Bűrmen cb944fdb7a icvgs, icvds, and icvbs should be IOP. 2025-07-29 10:51:39 +02:00
Árpád Bűrmen 56ecfa9e69 BSIM3 3.3.0 undeclared instance IC parameters. 2025-07-29 10:51:26 +02:00
Árpád Bűrmen 2c76daf2d1 MESFET m and ic parameters fixed. 2025-07-29 10:51:05 +02:00
Árpád Bűrmen 87aecbcba7 dtemp bug fixed. 2025-07-29 10:50:35 +02:00
Holger Vogt 619d6ae521 Prevent from endless loop if step evaluates to 0. 2025-07-29 10:50:23 +02:00
Holger Vogt 51d0e3d910 Add error checking when parsing the .dc or dc commands. 2025-07-29 10:50:06 +02:00
Holger Vogt dd1690521c Fix a bug: do not read in front of string s by s[-1]. 
Still needs more checking: we remmove and add 'params:'?
 2025-07-29 10:49:49 +02:00
Holger Vogt 9c1714d2f5 typo 2025-07-29 10:49:22 +02:00
Holger Vogt 508ab3bd8c New CPPDUALS: re-enable compiling with CYGWIN 2025-07-29 10:48:46 +02:00
Holger Vogt 7f8f510e91 add missing makefile.am, copied from previous cppduals/duals 2025-07-29 10:48:31 +02:00
Holger Vogt 6af3cfac72 New cppduals from https://gitlab.com/tesch1/cppduals 
downloaded may 1st, 2025
 2025-07-29 10:48:21 +02:00
Holger Vogt d2ded9fa2c Tiny modifications of SEE examples 2025-07-29 10:47:32 +02:00
Holger Vogt 3fb1ea1c39 Unix line endings 
rusage added
 2025-07-29 10:46:39 +02:00
Holger Vogt 9d7db2166a New example for seegen: CMOS comparator 2025-07-29 10:46:18 +02:00
Holger Vogt a4510f488f Add ouput 'mon' 2025-07-29 10:46:05 +02:00
Holger Vogt ea5979d391 No autostart when ctrl is set. 
Fix a bug when repeating the sequence.
 2025-07-29 10:45:50 +02:00
Holger Vogt 07f8c3558b Add a monitoring output the the seegen instance 2025-07-29 10:45:30 +02:00
Holger Vogt b628032d7d Add a generator for SEE (single event effects) pulses as a code model. 
To be used like
aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d')
see README.SEEgenerator for details
 2025-07-29 10:39:58 +02:00
Holger Vogt 878d7e1ff9 Add function cm_get_neg_node_name 
as cm_get_node_name delivers only the pos node.
 2025-07-29 10:39:47 +02:00
Giles Atkinson 5c4f151c6d Snapshot support for new statistics added by e1677a18c4. 
That prevents a crash exiting examples/snapshot/adder_snload.script.
 2025-07-29 10:39:00 +02:00
Giles Atkinson 95fc95771a Fix Bug #793 - "breakp.c error: compling without XSPICE failed". 
Additional changes to conditional compilation are needed for
iplot without XSPICE.
 2025-07-29 10:38:42 +02:00
Holger Vogt 9c4a54ffb7 Enable real (from fft)or complex (from sp) frequency vetors in plot sp 2025-07-29 10:38:17 +02:00
Holger Vogt f73873c495 Enable expressions in a meas statement within a .control section, like 
meas tran yeval2 FIND v(2) WHEN v(1)= 0.9*v(2)
 2025-07-29 10:37:59 +02:00
Holger Vogt 3464f4af2c Linux line endings 2025-07-29 10:37:02 +02:00
Brian Taylor 2eefdcdcff Merge branch 'pre-master-45' into bt_dev 2025-07-19 09:45:17 -07:00
Brian Taylor b516d0b4a9 Allocating arrays of double* should use sizeof double* not double, even though they may be the same. Avoid potential divide by zero. 2025-07-18 23:09:38 +02:00
Brian Taylor 4cf4b70c67 Fix memory leak in xspice oneshot. 2025-07-18 23:09:07 +02:00
Brian Taylor c9bd5bebbf Fix the xspice transmission_line examples. 
Also, cherry pick:
commit 87d09def9c (origin/bt_dev)
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Sun May 18 14:01:47 2025 -0700

    Fix memory leak in xspice oneshot.
 2025-07-16 17:29:02 +02:00
Brian Taylor 5b712f8265 Fix the xspice transmission_line examples. 
Also, cherry pick:
commit 87d09def9c (origin/bt_dev)
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Sun May 18 14:01:47 2025 -0700

    Fix memory leak in xspice oneshot.
 2025-07-15 14:16:55 -07:00
Brian Taylor 779a14490b Make inpcom.c the same as on branch pre-master-45. 2025-07-15 13:37:18 -07:00
Brian Taylor 11d560ed64 Merge branch 'pre-master-45' into bt_dev 2025-07-15 13:27:12 -07:00
dwarning 1618f71f49 bsim4 update to version 4.8.3 2025-07-15 18:05:03 +02:00
Vadim Kuznetsov e3e4906b12 Fix licence header in msline_common 2025-07-13 17:55:35 +03:00
b'Holger Vogt 18f6efe2f6 Merge /u/ra3xdh/ngspice/ branch xspice_tlines_rebased into pre-master-45 
https://sourceforge.net/p/ngspice/ngspice/merge-requests/33/
 2025-07-13 13:49:28 +00:00
Holger Vogt f954772f64 retain type=0, type=1, type=+1, or type=-1 in a .model card, 
even if compatmode PS or LT are set.
 2025-07-13 11:55:30 +02:00
Vadim Kuznetsov 1cac0ff6d6 Added MSOPEN model 2025-07-10 20:54:57 +03:00
Vadim Kuznetsov f90f5172ac Implement rollback; fix memory management 2025-07-10 20:54:57 +03:00
Vadim Kuznetsov fe20d8a340 Add license header for new files 2025-07-10 20:54:50 +03:00
dwarning ef8858f7dc allow showmod command for verilog-a models - feature request #100 2025-07-04 17:26:28 +02:00
b'Dietmar Warning ffc36a68fb Merge /u/arpadbuermen/ngspice/ branch vadng-pre-45 into pre-master-45 
https://sourceforge.net/p/ngspice/ngspice/merge-requests/35/
 2025-07-03 18:51:42 +00:00
Holger Vogt 62d3e3a51d Prevent from endless loop if step evaluates to 0. 2025-06-28 16:07:42 +02:00
Holger Vogt 99ed8ceb66 Add error checking when parsing the .dc or dc commands. 2025-06-28 11:11:53 +02:00
Holger Vogt 005aad92d7 Fix a bug: do not read in front of string s by s[-1]. 
Still needs more checking: we remmove and add 'params:'?
 2025-06-27 17:20:34 +02:00
Holger Vogt 36edfd47c2 typo 2025-06-27 17:18:37 +02:00
Árpád Bűrmen 0654f477cb icvgs, icvds, and icvbs should be IOP. 2025-06-26 09:44:47 +02:00
Holger Vogt af7a600c20 Tiny modifications of SEE examples 2025-06-24 10:32:41 +02:00
Árpád Bűrmen ca0c52ba94 BSIM3 3.3.0 undeclared instance IC parameters. 2025-06-23 14:17:00 +02:00
Holger Vogt da0338ee5c New CPPDUALS: re-enable compiling with CYGWIN 2025-06-13 15:29:45 +02:00