d31568bd83
Add parsing and translation of the FREQ form of E-source devices,
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integrated with the existing parsing of AND/NAND/OR/NOR forms (inpcom.c).
For the implementation, add a new analog XSPICE code model, xfer.
Add an example to examples/sp.
2023-07-15 11:15:08 +02:00
585f13bd4a
Better visibility of the results
2023-07-15 11:11:48 +02:00
c7bb12d9d0
More info
2023-05-27 10:49:32 +02:00
5c8af9770b
Add rusage to measure simulation time.
2023-05-27 10:48:07 +02:00
2685df1b05
Add vto model parameter (the default has changed!), add .ic
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to ease op and immediately start oscillation.
2023-05-27 10:47:43 +02:00
a48cc44c7f
Example input file for 'iplot -w' option
2023-05-27 10:46:55 +02:00
a48b36ffc5
more realistic self-heating example
2023-05-27 10:39:55 +02:00
14a403e193
Use ~ on the input of a tristate buffer for INV3, and avoid creating an extra inverter. For ff/latch use ~ on set/reset and jkff clock inputs to avoid creating extra inverters.
2023-05-27 10:38:40 +02:00
33e17fa969
noise simulation examples
2023-04-02 22:56:49 +02:00
7f4eb1c7d8
Add examples of controlling auto-bridge behaviour
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with the "vcc" and "family" parameters.
2023-04-01 13:56:23 +02:00
6213145c94
.control section: atanh examples
2023-03-18 22:32:34 +01:00
c2fb32f98a
really run a dc simulation
2023-03-18 14:30:23 +01:00
d36c4b8772
Remove bulk simulation netlist from files
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needing a .control section.
2023-01-28 17:02:13 +01:00
8c98b70e45
Add input file dedicated to batch mode,
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to be run with
ngspice -b -r inv.out bsimbulk_inverter_bach.sp
2023-01-28 17:01:53 +01:00
512bcf6095
Remove unused folder
2023-01-28 17:01:37 +01:00
dbdbcf95c2
BSIMBULK example with locally adding osdi models
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by using the 'pre_osdi' command in a .control section
2023-01-28 17:01:22 +01:00
b9eef23eed
Update the example structure for OSDI/OpenVAF:
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all compiled models into lib/ngspice
spinit updated to load the models via command 'osdi'
local calls with 'pre_osdi' commanted out.
2023-01-27 16:08:17 +01:00
5bd45eeb87
The Roessler Attractor examples has been provided by
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Giles Atkinson, of course
2023-01-24 16:29:50 +01:00
16c7c407d4
Nice looking Roessler Attractor
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provided by A. Gillespie
2023-01-24 15:17:45 +01:00
cb5f9e9bdc
MOS example files updated and moved to its own directory
2023-01-24 15:17:31 +01:00
af9f25e985
Various filter examples using Laplace expression x_fer
2023-01-20 15:07:37 +01:00
bf580abf69
Add a simple example of using string-valued parameters.
2023-01-09 16:33:53 +01:00
01c211339c
Rename example file
2023-01-09 16:33:38 +01:00
4936fa2b1d
Add serial load to 74f524 example.
2023-01-09 16:33:10 +01:00
0cae4f0b6c
special ngbehavior needed
2023-01-09 16:31:01 +01:00
c7fd3bcaee
Add example for 74f524.
2023-01-09 16:30:42 +01:00
4bcd4daf55
Rename projetc to OR (OR-gate)
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Add new path (absolute, so has to be modified by any user)
2022-12-27 14:22:07 +01:00
b639ebae44
Rename examples for ECL OR gate
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Simulate OR gate faster TSTEP 0.1n -> 0.3n
2022-12-27 14:21:24 +01:00
3e27e640b5
Missing renaming: osdi_win --> osdi_libs
2022-12-27 14:19:58 +01:00
4f73f18f6d
Remove
2022-12-27 14:19:18 +01:00
69660ad387
Move adder_common.inc to be available for all test files.
2022-12-27 14:18:54 +01:00
bb9469a03a
Rename test_osdi_libs to osdi_libs
2022-12-27 14:14:01 +01:00
96608abbe2
Update with Semimod download page
2022-12-27 14:13:27 +01:00
157200aa86
Rename test_osdi_win to test_osdi_libs
2022-12-27 14:13:02 +01:00
a211a90e5a
Mextram models: plotting with thicker lines
2022-12-27 14:12:41 +01:00
ac73e6f7b7
Update to the examples for osdi
2022-12-27 14:12:10 +01:00
d7bdfe1a20
Re-add optional selection of Berkeley model parameters.
2022-12-19 12:43:55 +01:00
5ec6543dbb
Add log plots
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Add sim vs. Temp.
Add y-labels
2022-12-19 12:43:27 +01:00
e28d3feee0
Remove unused variable debarr.
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Add another example.
2022-12-11 15:39:10 +01:00
45574cecb2
derivative inside of .func
2022-12-11 15:38:49 +01:00
89a48e7d73
simple example for derivative in B source
2022-12-11 15:38:37 +01:00
082ae1603e
add linewidth for graphs
2022-12-11 15:36:57 +01:00
058e7a34f8
tiny update, typos, font size
2022-12-11 15:36:42 +01:00
7ff8f3773f
Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
2022-12-11 15:34:33 +01:00
cd883d23d6
Examples for 74*568 behavioral subckts.
2022-12-11 15:33:53 +01:00
5324319edb
Move digital examples to new locations
2022-12-11 15:33:08 +01:00
925dc55a73
rename example file
2022-12-11 15:28:23 +01:00
ca1974ff37
Examples moved to folder /various
2022-12-11 15:28:01 +01:00
751019b447
Examples for d_pwm and d_osc
2022-12-11 15:27:42 +01:00
4294f49968
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
2022-12-11 15:25:24 +01:00
Giles Atkinson
Holger Vogt
dwarning
Brian Taylor
h_vogt