Brian Taylor
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b67d895a7b
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Add support for PSpice DLYLINE.
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2023-08-05 10:34:16 -07:00 |
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Brian Taylor
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04b5abfa14
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For d0_eff, d0_gff timing models specify the 1.0e-12 minimum Xspice delay valuesrather than defaulting to 1ns.
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2023-08-01 14:37:20 -07:00 |
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Brian Taylor
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49f5f5134a
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Prevent crashes in udevices.c when malformed U* instances are present. This would happen with incorrectly written U* gates, ff, latches which do not conform to the PSpice specs. Instead, ERROR messages are output which, hopefully, will help a user to debug their subckt.
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2023-07-21 16:33:03 -07:00 |
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Brian Taylor
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bf2f38c8d3
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Allocate compound gate connectors where needed.
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2023-04-09 09:57:55 -07:00 |
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Brian Taylor
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0bf1a37432
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Create correct translations of degenerate compound gates with $d_hi/$d_lo inputs.
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2023-04-08 16:36:23 -07:00 |
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Brian Taylor
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4dd2ad8d21
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Use ~ on the input of a tristate buffer for INV3, and avoid creating an extra inverter. For ff/latch use ~ on set/reset and jkff clock inputs to avoid creating extra inverters.
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2023-04-01 10:28:04 -07:00 |
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Brian Taylor
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7e4f9146dc
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Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays.
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2023-03-17 07:18:12 -07:00 |
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Brian Taylor
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2dec3d2dc0
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The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE.
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2023-03-10 11:40:37 -08:00 |
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Brian Taylor
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d3c5a31571
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For a ugate timing model, when tphlXX/tplhXX is not found, set the fall/rise delay to zero (1.0e-12).
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2023-03-04 11:08:09 -08:00 |
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Brian Taylor
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8453e1d1a9
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74F550 and 74F551 have only fall delays on the inverters. Use the fall delay for both rise and fall.
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2023-03-03 12:48:02 -08:00 |
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Brian Taylor
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70b3eca708
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Prepare for inertial_delay model parameter.
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2023-03-02 17:40:15 -08:00 |
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Brian Taylor
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2a32f2ebd2
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Check current_subckt is set when printing TRANS_OUT.
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2023-03-02 12:19:53 -08:00 |
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Brian Taylor
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dcafbbcf90
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Add port directions when logicexp or pindly are present.
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2023-01-30 14:41:49 -08:00 |
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Brian Taylor
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da6a311260
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Remove delay ifdefs.
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2023-01-28 13:11:28 -08:00 |
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Brian Taylor
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df8b349085
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Remove dead code from previous commit.
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2023-01-27 07:35:56 -08:00 |
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Brian Taylor
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2db2b3416f
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For unspecified gate delays (logic and tristate gates), which PSpice would consider as zero, set the rise and fall delays to 1.e-12s (the minimum for Xspice). For dff, jkff, dlatch, and srlatch use the Xspice default 1.0ns for rise and fall delays. If the ngspice variable (ps_port_directions & 2) is true, write the translated subckt to stdout, with TRANS_OUT prefix, for debugging purposes. The user could edit and replace the translated subckt if desired.
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2023-01-26 15:49:18 -08:00 |
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Brian Taylor
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c72781584a
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ERROR messages should be printed to stderr.
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2023-01-09 12:23:38 -08:00 |
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Brian Taylor
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7af21d1f5f
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Fix some comments.
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2023-01-03 09:38:57 -08:00 |
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Brian Taylor
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f137cc0c5c
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Ensure that amatch output is not binary data.
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2022-12-27 20:48:53 -08:00 |
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Brian Taylor
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afcab5f907
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Add variable ps_udevice_exit. If set non-zero, ngspice will exit if there is an error processing f_logicexp or f_pindly.
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2022-12-27 14:42:23 -08:00 |
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Brian Taylor
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d35491fa8f
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Return errors from f_logicexp and f_pindly without calling exit.
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2022-12-26 21:47:38 -08:00 |
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Brian Taylor
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bda5d3f845
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Distinguish between set/reset delays when possible.
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2022-12-09 09:46:00 -08:00 |
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Brian Taylor
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afb5dcbffb
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Make it optional to use zl/zh/lz/hz delays for utgate.
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2022-12-08 17:15:34 -08:00 |
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Brian Taylor
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4054d4a580
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Avoid unnecessary calculations for utgate.
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2022-12-08 11:31:34 -08:00 |
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Brian Taylor
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74df1a1913
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For utgate timing models, if hl/lh are not present use zl/zh/lz/hz to give a more accurate tristate delay.
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2022-12-08 10:46:19 -08:00 |
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Brian Taylor
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d5cf918ce0
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More conservative delay estimates for timing model type ugff.
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2022-12-07 19:52:11 -08:00 |
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Brian Taylor
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e7a85f95f0
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For dff/jkff, obtain more conservative estimates for clk_delay, set_delay and reset_delay.
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2022-12-07 11:12:22 -08:00 |
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Brian Taylor
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5238d6f18a
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Rewrite extract_model_param.
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2022-12-04 10:39:47 +01:00 |
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Brian Taylor
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a317639d23
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Modify the delay calculation for non-conforming timing model in .subckt CD4572UB.
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2022-12-04 10:39:40 +01:00 |
Giles Atkinson
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b124749122
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Fix warnings from gcc 10.2.1.
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2022-11-28 22:34:23 +01:00 |
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Brian Taylor
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44c69f5bf5
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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2022-11-28 22:33:00 +01:00 |
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Brian Taylor
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1200092250
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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2022-11-07 14:47:18 +01:00 |
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Brian Taylor
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ab7634e72e
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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2022-11-07 14:47:13 +01:00 |
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Brian Taylor
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9d239dc2f7
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Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards.
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2022-11-07 14:45:57 +01:00 |
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Brian Taylor
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67369f1c67
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Initial logicexp parser and gate generator.
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2022-11-07 14:45:45 +01:00 |
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Brian Taylor
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db81d7ca28
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Add drive 0/1 for $d_lo/$d_hi.
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2022-11-07 14:45:33 +01:00 |
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Brian Taylor
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ff58fbbe56
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Remove VisualC compile warnings.
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2022-10-09 10:15:14 +02:00 |
Holger Vogt
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dcb3bf0f8b
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Prevent Visual Studio compiler warnings
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2022-10-08 17:20:48 +02:00 |
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Brian Taylor
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41b7c867ff
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Fix memory leaks in ff/latch code.
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2022-09-23 14:59:17 +02:00 |
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Brian Taylor
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93bd661a3e
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If ps_udevice_msgs >= 2, print complete line of unsupported PSpice instance. For debugging purposes.
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2022-09-23 14:59:01 +02:00 |
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Brian Taylor
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78f732a8a1
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Add comment about ps_udevice_msgs variable. Set to 1 will print PSpice instance names and types which are not supported and are found when processing a subckt.
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2022-09-14 15:01:39 +02:00 |
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Brian Taylor
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a361d63ca1
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Make a trivial change to support (n)and3a, (n)or3a, (n)xor3a types. These are not used in any of the Micro Cap libraries. Completes support for Pspice tristate gate types.
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2022-08-06 10:43:17 +02:00 |
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Brian Taylor
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f0876163e8
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If variable ps_port_directions >= 2, also show the translated Xspice statements.
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2022-08-06 10:43:02 +02:00 |
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Brian Taylor
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47753ad5b2
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Ignore IO models in a subckt. Setting variable ps_port_directions to a non-zero int prints the directions (IN, OUT, INOUT) of subckt ports.
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2022-08-06 10:42:50 +02:00 |
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Brian Taylor
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15d987ad0f
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Check for name collisions between nodes generated during translation from Pspice to Xspice and instance pin or subckt port names. These are reported as ERRRORs.
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2022-08-06 10:42:43 +02:00 |
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Brian Taylor
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ec6938ed70
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There needs to be 2 variants of d0_gff. One for d_dlatch, the other for d_srlatch.
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2022-07-01 15:55:26 +02:00 |
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Brian Taylor
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6418fe75b7
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Clean out dead code in model processing.
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2022-07-01 15:55:15 +02:00 |
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Brian Taylor
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4c2152c74f
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Add support for srff.
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2022-07-01 15:55:06 +02:00 |
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Brian Taylor
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b64f684a62
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Remove debug code.
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2022-07-01 15:55:00 +02:00 |
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Brian Taylor
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4d9f834f5e
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Remove invalid check.
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2022-07-01 15:54:45 +02:00 |