Commit Graph

364 Commits

Author SHA1 Message Date
Holger Vogt 95b21de8a1 Re-add optional selection of Berkeley model parameters. 2022-12-14 13:26:02 +01:00
h_vogt 831382cc7d Add log plots
Add sim vs. Temp.
Add y-labels
2022-12-13 21:07:27 +01:00
Holger Vogt 1b121307c8 Remove unused variable debarr.
Add another example.
2022-12-04 10:41:22 +01:00
Holger Vogt 2b412cf470 derivative inside of .func 2022-12-04 10:41:17 +01:00
Holger Vogt 288d60b8cb simple example for derivative in B source 2022-12-04 10:41:11 +01:00
Holger Vogt 91a5ceb722 add linewidth for graphs 2022-12-04 10:32:59 +01:00
Holger Vogt b5d0ed4590 tiny update, typos, font size 2022-12-04 10:32:32 +01:00
Brian Taylor 44c69f5bf5 Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 2022-11-28 22:33:00 +01:00
Brian Taylor de2280ca73 Examples for 74*568 behavioral subckts. 2022-11-28 22:32:53 +01:00
Holger Vogt 9fbf2acceb Move digital examples to new locations 2022-11-24 16:47:59 +01:00
Holger Vogt fcc3191732 rename example file 2022-11-12 14:52:22 +01:00
Holger Vogt 0ea6dd8322 Examples moved to folder /various 2022-11-12 14:49:01 +01:00
Holger Vogt 7cf6b1f12b Examples for d_pwm and d_osc 2022-11-12 14:47:57 +01:00
Brian Taylor b0e9874de8 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented. 2022-11-11 14:13:03 +01:00
Brian Taylor f9236131ff Typo, 2 x1 subcircuits. 2022-11-07 14:47:46 +01:00
Brian Taylor d05689eed8 Add pindly tristate example. Cleanup error handling. 2022-11-07 14:47:36 +01:00
Brian Taylor 1200092250 Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE. 2022-11-07 14:47:18 +01:00
Brian Taylor ab7634e72e Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly. 2022-11-07 14:47:13 +01:00
Holger Vogt dc8c7db718 Fix a bug in simple diode, when ilimit is set, but not epsilon.
Make model more similar to LTSPICE
Add an example
2022-09-29 16:14:25 +02:00
Giles Atkinson c75476eaa0 Add some automatic bridge examples, mostly using the bidirectional bridge. 2022-09-23 13:15:07 +02:00
Holger Vogt fb75a15e83 example for pwlts source code model 2022-09-09 15:26:45 +02:00
Holger Vogt 0be7461dd9 Enable power measurement for W switch 2022-08-29 20:30:23 +02:00
Holger Vogt c70a438ae0 Replace end-of-line comment delimiter $ by ;
So to make it independent from compatibility switch selection.
2022-08-29 14:19:47 +02:00
Holger Vogt 6b786099cb examples for .probe alli or .probe i(xx) 2022-08-29 14:11:20 +02:00
Holger Vogt ef3adfc050 set colors for grids and data 2022-08-28 17:52:55 +02:00
Brian Taylor 0e0daa7d9a Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test. 2022-08-06 10:42:56 +02:00
Holger Vogt 03bd381e83 aswitch needs two input nodes because gd has been selected for input. 2022-08-05 17:30:51 +02:00
Holger Vogt 3fc3997cef Handle the case when control voltages on and off are equal.
Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
2022-08-05 17:30:08 +02:00
Holger Vogt 227bb9c419 If a node name to be plotted ends by ':power', its type is set to POWER.
Thus 'settype power nodename(s)' in the examples is no longer necessary.
2022-07-31 15:49:50 +02:00
Holger Vogt 7970bc7c54 New tables for MOS devices 2022-07-24 15:55:46 +02:00
Holger Vogt 9302f14bb9 Return data to input directory. 2022-07-24 15:54:58 +02:00
Holger Vogt 09e48350eb Simplify the NMOS or PMOS selection by setting only one parameter
'mostype'
ngspice-37+ is required.
2022-07-24 15:51:59 +02:00
Brian Taylor b64f684a62 Remove debug code. 2022-07-01 15:55:00 +02:00
Brian Taylor 831f8b1dad This test is equivalent to examples/xspice/xspice_c3.cir and uses Pspice subckts for the divider and nand gate. 2022-07-01 15:53:10 +02:00
Brian Taylor 3ca14e44ed Add counter test. Check for usage of $d_lo, $d_hi, $d_nc usage with dff, jkff, dltch which will not translate to Xspice. 2022-07-01 15:53:02 +02:00
Brian Taylor 45c88edb77 All-digital U* device examples. No a/d or d/a interfaces on the subcircuits. 2022-07-01 15:52:52 +02:00
Holger Vogt 140d143ae8 Update, link on device models (public domain or TI)
Download adresses for TI models.
2022-05-16 16:31:15 +02:00
Giles Atkinson 2821b24350 Fix filename case. 2022-05-09 10:51:26 +02:00
Holger Vogt 622a9fdd04 New example: S-parameters of a Tschebyschef Low Pass filter 2022-05-03 17:07:40 +02:00
Holger Vogt b107312544 New example for power measurement with .probe 2022-05-03 17:05:45 +02:00
Holger Vogt 1d8dacedaa S-parameters: Replace S11 by S_1_1 etc. to avoid ambiguity
when more than 10 ports are measured.
Update to S-parameter script and command wr2sp
2022-04-28 11:58:21 +02:00
Holger Vogt 429cba6593 Add .probe p(...) commands (including plotting and averaging) 2022-04-25 15:19:08 +02:00
Holger Vogt 9ac358fbf5 Add measuring power of the VDMOS devices with .probe p(device) 2022-04-25 13:39:23 +02:00
Holger Vogt b7d811c306 Improve printout formatting 2022-04-06 15:58:31 +02:00
Holger Vogt 7a50c4b84a examples for loops.
The syntax is listed in the ngspice manual,
chapter 17.6 Control Structures. Practical examples
using a simple voltage divider circuit are given here.
2022-04-06 10:32:18 +02:00
Holger Vogt b2923ee7ff New examples: command 'sp' and three-port example 2022-03-29 15:51:04 +02:00
Holger Vogt 7de6d65e6d Fix internet address 2022-03-21 16:51:12 +01:00
Holger Vogt 9be02e7334 Replace (all) by alli 2022-03-14 11:05:10 +01:00
Holger Vogt 7f2229f024 replace (all) by alli 2022-03-14 10:58:05 +01:00
Holger Vogt e61c92af5a save only relevant digital data (command 'esave' 2022-02-26 11:06:39 +01:00