h_vogt
|
c3c7adf099
|
reset clipping
|
2017-07-06 15:21:43 +02:00 |
|
h_vogt
|
2c705fbbdc
|
update to existing examples (for improved readability)
|
2017-07-06 12:14:38 +02:00 |
|
h_vogt
|
d48ea30348
|
new pll examples, evalute step in divisor parameter
|
2017-07-06 12:14:04 +02:00 |
|
h_vogt
|
5d0c3182d3
|
add BSIM3 model parameters for loop filer with transistor charge pump
|
2012-08-05 20:15:53 +02:00 |
dwarning
|
96dd397251
|
correct the plot output
|
2012-08-05 12:06:11 +02:00 |
|
h_vogt
|
19a67fb7c5
|
pll: just include one of the two vco available
(avoid a bug which has been removed only recently)
|
2012-08-04 00:22:25 +02:00 |
|
h_vogt
|
a0db6f0ccd
|
update to XSPICE phase-locked loop example
|
2012-08-03 23:22:54 +02:00 |
|
h_vogt
|
6cd13e0475
|
pll-xspice-fstep.cir: pll with ref frequency steps
|
2012-07-31 18:05:10 +02:00 |
|
h_vogt
|
c31fc334f6
|
pll-xspice.cir: save command added
|
2012-07-31 17:31:28 +02:00 |
|
h_vogt
|
c0b5a78097
|
new XSPICE example: use trtol=1
less ripple, but longer simulation time
|
2012-07-30 00:01:56 +02:00 |
|
h_vogt
|
85ece25a3a
|
new XSPICE example: mixed mode pll circuit
|
2012-07-29 13:52:23 +02:00 |