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PULSE: correct timing in case of phase != 0

This commit is contained in:
h_vogt 2010-11-21 21:06:00 +00:00
parent 4ab496dd1b
commit f21f2a05bc
2 changed files with 2 additions and 10 deletions
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7
src/spicelib/devices/vsrc/vsrcacct.c
View File

@ -78,17 +78,12 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
/* normalize phase to 0 - 360° */
/* normalize phase to cycles */
phase = PHASE / 360.0;
if (phase >=0)
phase -= floor(phase);
else
phase -= ceil(phase);
phase = fmod(phase, 1.0);
deltat = phase * PER;
while (deltat > 0)
deltat -= PER;
time += deltat;
tshift = TD - deltat;
while (tshift < 0)
tshift += PER;
#endif
/* gtri - end - wbk - add PHASE parameter */

5
src/spicelib/devices/vsrc/vsrcload.c
View File

@ -97,10 +97,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
/* normalize phase to cycles */
phase = PHASE / 360.0;
if (phase >=0)
phase -= floor(phase);
else
phase -= ceil(phase);
phase = fmod(phase, 1.0);
deltat = phase * PER;
while (deltat > 0)
deltat -= PER;