From f21f2a05bc1ca4821fa50168cc8febc5eae952e1 Mon Sep 17 00:00:00 2001
From: h_vogt <h_vogt>
Date: Sun, 21 Nov 2010 21:06:00 +0000
Subject: [PATCH]  PULSE:  correct timing in case of phase != 0

---
 src/spicelib/devices/vsrc/vsrcacct.c | 7 +------
 src/spicelib/devices/vsrc/vsrcload.c | 5 +----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/spicelib/devices/vsrc/vsrcacct.c b/src/spicelib/devices/vsrc/vsrcacct.c
index d5a02a747..60a56c18f 100644
--- a/src/spicelib/devices/vsrc/vsrcacct.c
+++ b/src/spicelib/devices/vsrc/vsrcacct.c
@@ -78,17 +78,12 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
 		         /* normalize phase to 0 - 360° */ 
 		         /* normalize phase to cycles */
                     phase = PHASE / 360.0;
-                    if (phase >=0) 
-                        phase -= floor(phase);
-                    else  
-                        phase -= ceil(phase);
+                    phase = fmod(phase, 1.0);
                     deltat =  phase * PER;
                     while (deltat > 0) 
                         deltat -= PER;
                     time += deltat;
                     tshift = TD - deltat; 
-                    while (tshift < 0) 
-                        tshift += PER;
 #endif		    
 /* gtri - end - wbk - add PHASE parameter */			
 		   		   
diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c
index 45e79ac40..f730a71e4 100644
--- a/src/spicelib/devices/vsrc/vsrcload.c
+++ b/src/spicelib/devices/vsrc/vsrcload.c
@@ -97,10 +97,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
 
 		            /* normalize phase to cycles */
                     phase = PHASE / 360.0;
-                    if (phase >=0) 
-                        phase -= floor(phase);
-                    else  
-                        phase -= ceil(phase);
+                    phase = fmod(phase, 1.0);
                     deltat =  phase * PER;
                     while (deltat > 0) 
                         deltat -= PER;