up, where to ? fixme, there are more ...
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@ -41,7 +41,7 @@ VDMOSacLoad(GENmodel *inModel, CKTcircuit *ckt)
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xrev=0;
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}
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/*
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* meyer's model parameters
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* VDMOS cap model parameters
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*/
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capgs = ( *(ckt->CKTstate0+here->VDMOScapgs)+
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*(ckt->CKTstate0+here->VDMOScapgs));
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