reduce simulation time for tcl examples

2026-08-22 13:57:32 +02:00 · 2017-10-12 11:22:17 +02:00
parent af7ab797c2
commit 8539029e6d
2 changed files with 2 additions and 2 deletions
@@ -579,5 +579,5 @@ EVLOGIC VRAMP 0 VSLEW 0 2.5
 VDDPOWER VDD VRAMP DC 0
 VARACTOR_V VARACTOR_V 0 DC 2.5

-.TRAN 0.02n 3000n 0n 0.5n 
+.TRAN 0.02n 100n 0n 0.5n 
 .END