correct init for convergence test

2019-03-07 23:29:09 +01:00 · 2019-03-07 23:29:09 +01:00 · 7966aa36ae
parent 3494e6b390
commit 7966aa36ae
1 changed files with 1 additions and 1 deletions
--- a/src/spicelib/devices/vbic/vbicload.c
+++ b/src/spicelib/devices/vbic/vbicload.c
@ -739,7 +739,7 @@ VBICload(GENmodel *inModel, CKTcircuit *ckt)
                /*
                 *   limit nonlinear branch voltages
                 */
-                ichk1 = 1;
+                ichk1 = 1, ichk2 = 1, ichk3 = 1, ichk4 = 1, ichk5 = 1;
                Vbei = DEVpnjlim(Vbei,*(ckt->CKTstate0 + here->VBICvbei),vt,
                        here->VBICtVcrit,&icheck);
                Vbex = DEVpnjlim(Vbex,*(ckt->CKTstate0 + here->VBICvbex),vt,