From 7966aa36ae03bf7a8a003604f318a674508fc9f3 Mon Sep 17 00:00:00 2001
From: dwarning <dwarning>
Date: Thu, 7 Mar 2019 23:29:09 +0100
Subject: [PATCH] correct init for convergence test

---
 src/spicelib/devices/vbic/vbicload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/spicelib/devices/vbic/vbicload.c b/src/spicelib/devices/vbic/vbicload.c
index 82793ecaa..03d4916d7 100644
--- a/src/spicelib/devices/vbic/vbicload.c
+++ b/src/spicelib/devices/vbic/vbicload.c
@@ -739,7 +739,7 @@ VBICload(GENmodel *inModel, CKTcircuit *ckt)
                 /*
                  *   limit nonlinear branch voltages
                  */
-                ichk1 = 1;
+                ichk1 = 1, ichk2 = 1, ichk3 = 1, ichk4 = 1, ichk5 = 1;
                 Vbei = DEVpnjlim(Vbei,*(ckt->CKTstate0 + here->VBICvbei),vt,
                         here->VBICtVcrit,&icheck);
                 Vbex = DEVpnjlim(Vbex,*(ckt->CKTstate0 + here->VBICvbex),vt,