History

Josef Gajdusek 0a8a848a72 Minor UX improvements to the generic example code (#1706 ) * generic: Fix Python path not including the examples/ directory in the example It seems that at some point, the embedded Python stopped including the directory that nextpnr-generic was executed in inside of its sys.path. This likely happened by `de3d5be8` specifying an explicit argv to the interpreter init function. * generic: Improve the example for K != 4 Configuring K < 4 used to result in "dangling" inputs to the cells being generated (those are just not driven by anything in the resulting Verilog/JSON). Configuring K > 4 used to result in an assertion crash in cells.cc. The ctx.setLutK call fixes both cases.		2026-04-28 13:08:44 +02:00
..
.gitignore	generic: Add support for post-PnR simulation	2019-11-27 15:17:53 +00:00
README.md	generic/examples: Add FASM writer Python script	2019-04-17 11:00:23 +01:00
__init__.py	generic/examples: Add FASM writer Python script	2019-04-17 11:00:23 +01:00
bitstream.py	return FF_USED, formatting, correct INIT	2019-11-08 17:15:12 +01:00
blinky.v	generic: Add support for post-PnR simulation	2019-11-27 15:17:53 +00:00
blinky_tb.v	generic: Add support for post-PnR simulation	2019-11-27 15:17:53 +00:00
simple.py	Minor UX improvements to the generic example code (#1706 )	2026-04-28 13:08:44 +02:00
simple.sh	Minor UX improvements to the generic example code (#1706 )	2026-04-28 13:08:44 +02:00
simple_config.py	generic/examples: Add FASM writer Python script	2019-04-17 11:00:23 +01:00
simple_timing.py	dedicated output for LUT in GENERIC_SLICE	2019-11-08 15:54:27 +01:00
simtest.sh	Minor UX improvements to the generic example code (#1706 )	2026-04-28 13:08:44 +02:00
write_fasm.py	generic: Refactor for faster performance	2021-12-30 11:54:08 +00:00

README.md

Generic Architecture Example

This contains a simple, artificial, example of the nextpnr generic API.

simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles
simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)
write_fasm.py uses the nextpnr Python API to write a FASM file for a design
bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design
Run simple.sh to build an example design on the FPGA above