Minor UX improvements to the generic example code (#1706)

* generic: Fix Python path not including the examples/ directory in the example

It seems that at some point, the embedded Python stopped including the
directory that nextpnr-generic was executed in inside of its sys.path.
This likely happened by de3d5be8 specifying an explicit argv to
the interpreter init function.

* generic: Improve the example for K != 4

Configuring K < 4 used to result in "dangling" inputs to the cells being
generated (those are just not driven by anything in the resulting Verilog/JSON).

Configuring K > 4 used to result in an assertion crash in cells.cc.

The ctx.setLutK call fixes both cases.
This commit is contained in:
Josef Gajdusek 2026-04-28 13:08:44 +02:00 committed by GitHub
parent 3c29cc217e
commit 0a8a848a72
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3 changed files with 8 additions and 2 deletions

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@ -3,6 +3,8 @@ from simple_config import *
def is_io(x, y):
return x == 0 or x == X-1 or y == 0 or y == Y-1
ctx.setLutK(K)
for x in range(X):
for y in range(Y):
# Bel port wires

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@ -1,5 +1,7 @@
#!/usr/bin/env bash
set -ex
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
export PYTHONPATH=$(dirname $0)
K=$(python3 -c "import simple_config; print(simple_config.K)")
yosys -p "tcl ../synth/synth_generic.tcl $K blinky.json" blinky.v
${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"

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@ -1,6 +1,8 @@
#!/usr/bin/env bash
set -ex
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
export PYTHONPATH=$(dirname $0)
K=$(python3 -c "import simple_config; print(simple_config.K)")
yosys -p "tcl ../synth/synth_generic.tcl $K blinky.json" blinky.v
${NEXTPNR:-../../nextpnr-generic} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v