mirror of https://github.com/YosysHQ/nextpnr.git
abb52f81c2
* Check SER_CLK more * Use connectPorts * move rewire code * Move data structures * move placement decision for later * cleanups * find working layout * clangformat * Inverted input on ODDR * Fix some tests * Copy clocks for multi die * cleanup * reporting * bugfix * handle PLL special inputs * Fix user globals * Proper DDR per bank and cleanup * Add extra data for die regions and create them * Better forced_die implementation * Copy region to newly generated cells, and update when constrained * Update PLL error messages * Add TODO comment |
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| gowin | ||
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| xilinx | ||