* gatemate: add alternate clock routes
* use additional pins
* Fix clock router and timings
* Fix DDR nets
* Test passtrough concept
* remove not used variable
* wip
* handle pip masks
* Cleanup
* create CPE_CPLINES cells and set properties on them
* Fix pip masking
* rough code to break cplines into subnets
* add ports to cell
* mux bridges need cell bel pins too
* fix multiplier output register packing
* remove empty if
* Fix ODDR
* Add options to disable some pips
* Use resources info
* mask field to resource field
* produce valid netlist with propagation netlist at least
* adapt reassign_cplines for internal resource pips
* Handle block and resources
* fix formatting
* It is required to set all mandatory properties now
* arch API for resources
* current progress
* Add option to skip bridges
* perform per-wire resource congestion costing
* Added no-cpe-cp option
* resource bugfix
* comment out spammy debug message
* Fix routing conflicts issues
* allow only some pass trough for clock router
* handle inversion bits for pass signals
* verify inversion before/after assigning bridges
* we care only if there is net
* Revert "we care only if there is net"
This reverts commit 3da2769e31.
* Revert "verify inversion before/after assigning bridges"
This reverts commit 8613ee17c8.
* chipdb version bump
* clangformat
* cleanup
* cleanup
* Initial conversion to GroupId
* Keep group info in pip extra
* Cleanup headers
* Initialize resource efficiently
* Addressing review comments
* improve resource docs
* Make CP lines not use as clocks as default
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Co-authored-by: Lofty <dan.ravensloft@gmail.com>
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