mirror of https://github.com/YosysHQ/nextpnr.git
a28d554eec
In some cases, wires with the same name were being re-created. This affected both the creation of shared primitive ports and changing the wire type if the cell had an additional function. Here, we separate wire creation and type change into a separate function and use it in most cases. Addresses: https://github.com/YosysHQ/nextpnr/issues/1759 Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||