mirror of https://github.com/YosysHQ/nextpnr.git
Gowin. Fix wire IDs leak.
In some cases, wires with the same name were being re-created. This affected both the creation of shared primitive ports and changing the wire type if the cell had an additional function. Here, we separate wire creation and type change into a separate function and use it in most cases. Addresses: https://github.com/YosysHQ/nextpnr/issues/1759 Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit
parent
8945407874
commit
a28d554eec
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@ -512,6 +512,15 @@ def uturn(db: chipdb, x: int, y: int, wire: str):
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wire = f'{direction}{num}{segment}'
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return (x, y, wire)
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def create_reuse_wire(tt: TileType, name: str, wire_type: str="", const_value: str=""):
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""" Whenever possible, use an existing wire. This situation arises when
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creating ports for primitives that share a wire (for example, for RESET)
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when located in the same tile. """
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if not tt.has_wire(name):
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tt.create_wire(name, wire_type, const_value)
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elif wire_type:
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tt.set_wire_type(name, wire_type)
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def create_nodes(chip: Chip, db: chipdb):
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# : (x, y)
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dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
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@ -576,10 +585,7 @@ def create_nodes(chip: Chip, db: chipdb):
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min_wire_name_len = len(next(iter(node))[2])
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for y, x, wire in node:
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if wire_type:
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if not chip.tile_type_at(x, y).has_wire(wire):
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chip.tile_type_at(x, y).create_wire(wire, wire_type)
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else:
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chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
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create_reuse_wire(chip.tile_type_at(x, y), wire, wire_type)
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new_node = NodeWire(x, y, wire)
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gl_nodes = global_nodes.setdefault(node_name, [])
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if new_node not in gl_nodes:
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@ -636,11 +642,9 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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return
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# hclk wires
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for dst, srcs in db.hclk_pips[y, x].items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, "HCLK")
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create_reuse_wire(tt, dst, "HCLK")
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "HCLK")
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create_reuse_wire(tt, src, "HCLK")
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tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
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hclk_bel_zs = {
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@ -703,8 +707,7 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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osc_type = desc['type']
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portmap = db[y, x].bels[osc_type].portmap
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, port)
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create_reuse_wire(tt, wire, port)
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bel = tt.create_bel(osc_type, osc_type, z = OSC_Z)
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for port, wire in portmap.items():
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if 'OUT' in port:
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@ -713,21 +716,18 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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elif func == 'gsr':
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wire = desc['wire']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
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tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
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elif func == 'bandgap':
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wire = desc['wire']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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bel = tt.create_bel("BANDGAP", "BANDGAP", z = BANDGAP_Z)
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tt.add_bel_pin(bel, "BGEN", wire, PinType.INPUT)
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elif func == 'dhcen':
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for idx, dhcen in enumerate(desc):
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wire = dhcen['ce']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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bel_z = DHCEN_Z + idx
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bel = tt.create_bel(f"DHCEN{idx}", "DHCEN", z = bel_z)
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tt.add_bel_pin(bel, "CE", wire, PinType.INPUT)
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@ -738,12 +738,10 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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bel_z = DLLDLY_Z + idx
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bel = tt.create_bel(f"DLLDLY{idx}", "DLLDLY", z = bel_z)
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for pin, wire in dlldly['in_wires'].items():
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, pin, wire, PinType.INPUT)
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for pin, wire in dlldly['out_wires'].items():
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, pin, wire, PinType.OUTPUT)
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io_dlldly_bels[f"{dlldly['io_loc']}/{dlldly['io_bel']}"] = f"X{x}Y{y}/DLLDLY{idx}"
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@ -753,13 +751,11 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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bel = tt.create_bel(f"DQCE{idx}", "DQCE", bel_z)
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wire = desc[idx]['clkin']
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dqce_bels[wire] = (x, y, bel_z)
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if not tt.has_wire(wire):
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tt.create_wire(wire, "GLOBAL_CLK")
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create_reuse_wire(tt, wire, "GLOBAL_CLK")
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tt.add_bel_pin(bel, "CLKIN", wire, PinType.INPUT)
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tt.add_bel_pin(bel, "CLKOUT", wire, PinType.OUTPUT)
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wire = desc[idx]['ce']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, "CE", wire, PinType.INPUT)
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elif func == 'dcs':
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for idx in range(2):
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@ -771,25 +767,21 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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bel_z = DCS_Z + idx
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bel = tt.create_bel(f"DCS{idx}", "DCS", bel_z)
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wire = desc[idx]['clkout']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, "CLKOUT", wire, PinType.OUTPUT)
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clkout_wire = wire
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for clk_idx, wire in enumerate(desc[idx]['clk']):
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if not tt.has_wire(wire):
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tt.create_wire(wire, "GLOBAL_CLK")
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create_reuse_wire(tt, wire, "GLOBAL_CLK")
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tt.add_bel_pin(bel, f"{dcs_prefix}{clk_idx}", wire, PinType.INPUT)
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# This is a fake PIP that allows routing “through” this
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# primitive from the CLK input to the CLKOUT output.
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tt.create_pip(wire, clkout_wire)
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dcs_bels[wire] = (x, y, bel_z)
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for i, wire in enumerate(desc[idx]['clksel']):
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, f"CLKSEL{i}", wire, PinType.INPUT)
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wire = desc[idx]['selforce']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, "SELFORCE", wire, PinType.INPUT)
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elif func == 'io16':
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role = desc['role']
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@ -804,11 +796,10 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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for port, wire in portmap.items():
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if port == 'FCLK': # XXX compatibility
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wire = 'FCLKA'
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if not tt.has_wire(wire):
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if port in {'CLK', 'PCLK'}:
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tt.create_wire(wire, "TILE_CLK")
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else:
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tt.create_wire(wire, "IOL_PORT")
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if port in {'CLK', 'PCLK'}:
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create_reuse_wire(tt, wire, "TILE_CLK")
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else:
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create_reuse_wire(tt, wire)
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if 'OUT' in port:
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tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
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else:
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@ -820,25 +811,21 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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elif func == 'mipi_ibuf':
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bel = tt.create_bel('MIPI_IBUF', 'MIPI_IBUF', MIPIIBUF_Z)
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wire = desc['HSREN']
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, 'HSREN', wire, PinType.INPUT)
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wire = 'MIPIOL'
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, 'OL', wire, PinType.OUTPUT)
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for i in range(2):
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wire = f'MIPIEN{i}'
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if not tt.has_wire(wire):
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tt.create_wire(wire)
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create_reuse_wire(tt, wire)
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tt.add_bel_pin(bel, f'MIPIEN{i}', wire, PinType.INPUT)
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elif func == 'buf':
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for buf_type, wires in desc.items():
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for i, wire in enumerate(wires):
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if not tt.has_wire(wire):
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tt.create_wire(wire, "TILE_CLK")
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create_reuse_wire(tt, wire, "TILE_CLK")
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wire_out = f'{buf_type}{i}_O'
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tt.create_wire(wire_out, "BUFG_O")
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create_reuse_wire(tt, wire_out, "BUFG_O")
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# XXX make Z from buf_type
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bel = tt.create_bel(f'{buf_type}{i}', buf_type, z = BUFG_Z + i)
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bel.flags = BEL_FLAG_GLOBAL
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@ -848,86 +835,81 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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bel = tt.create_bel("USERFLASH", desc['type'], USERFLASH_Z)
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portmap = desc['ins']
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, "FLASH_IN")
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create_reuse_wire(tt, wire, "FLASH_IN")
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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portmap = desc['outs']
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, "FLASH_OUT")
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create_reuse_wire(tt, wire, "FLASH_OUT")
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tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
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elif func == 'emcu':
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bel = tt.create_bel("EMCU", "EMCU", EMCU_Z)
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portmap = desc['ins']
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, "EMCU_IN")
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create_reuse_wire(tt, wire, "EMCU_IN")
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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portmap = desc['outs']
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, "EMCU_OUT")
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create_reuse_wire(tt, wire, "EMCU_OUT")
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tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
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elif func == 'pincfg':
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bel = tt.create_bel("PINCFG", "PINCFG", PINCFG_Z)
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portmap = desc['ins']
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, "PINCFG_IN")
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create_reuse_wire(tt, wire, "PINCFG_IN")
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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elif func == 'pll':
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pll = tt.create_bel("PLL", "PLLA", z = PLL_Z)
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pll.flags = BEL_FLAG_GLOBAL
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for pin, wire in desc['outputs'].items():
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tt.create_wire(wire, "PLL_O")
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create_reuse_wire(tt, wire, "PLL_O")
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tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
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for pin, wire in desc['inputs'].items():
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tt.create_wire(wire, "PLL_I")
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create_reuse_wire(tt, wire, "PLL_I")
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tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
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elif func == 'adc':
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pll = tt.create_bel("ADC", "ADC", z = ADC_Z)
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for pin, wire in desc['outputs'].items():
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tt.create_wire(wire, "ADC_O")
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create_reuse_wire(tt, wire, "ADC_O")
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tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
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for pin, wire in desc['inputs'].items():
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if pin == 'CLK' or pin == 'MDRP_CLK':
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tt.create_wire(wire, "TILE_CLK")
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create_reuse_wire(tt, wire, "TILE_CLK")
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else:
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tt.create_wire(wire, "ADC_I")
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create_reuse_wire(tt, wire, "ADC_I")
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tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
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elif func == 'gnd_source':
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# GND is the logic low level generator
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tt.create_wire('VSS', 'GND', const_value = 'VSS')
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create_reuse_wire(tt, 'VSS', 'GND', const_value = 'VSS')
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gnd = tt.create_bel('GND', 'GND', z = GND_Z)
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tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
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elif func == 'vcc_source':
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# VCC is the logic high level generator
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tt.create_wire('VCC', 'VCC', const_value = 'VCC')
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create_reuse_wire(tt, 'VCC', 'VCC', const_value = 'VCC')
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gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
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tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
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elif func == 'clkdiv2':
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for i, pins in desc['bels'].items():
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clkdiv2 = tt.create_bel(f"CLKDIV2_{i}", "CLKDIV2", z = CLKDIV2_0_Z + i)
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for pin, wire in pins['outputs'].items():
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tt.create_wire(wire, "HCLK")
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create_reuse_wire(tt, wire, "HCLK")
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tt.add_bel_pin(clkdiv2, pin, wire, PinType.OUTPUT)
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for pin, wire in pins['inputs'].items():
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if pin == 'RESETN':
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tt.create_wire(wire, "")
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create_reuse_wire(tt, wire, "")
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else:
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tt.create_wire(wire, "HCLK")
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create_reuse_wire(tt, wire, "HCLK")
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tt.add_bel_pin(clkdiv2, pin, wire, PinType.INPUT)
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elif func == 'clkdiv':
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for i, pins in desc['bels'].items():
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clkdiv = tt.create_bel(f"CLKDIV_{i}", "CLKDIV", z = CLKDIV_0_Z + i)
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for pin, wire in pins['outputs'].items():
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tt.create_wire(wire, "HCLK")
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create_reuse_wire(tt, wire, "HCLK")
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tt.add_bel_pin(clkdiv, pin, wire, PinType.OUTPUT)
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for pin, wire in pins['inputs'].items():
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if pin in {'RESETN', 'CALIB'}:
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tt.create_wire(wire, "")
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create_reuse_wire(tt, wire, "")
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else:
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tt.create_wire(wire, "HCLK")
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create_reuse_wire(tt, wire, "HCLK")
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tt.add_bel_pin(clkdiv, pin, wire, PinType.INPUT)
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def set_wire_flags(tt: TileType, tdesc: TypeDesc):
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@ -1033,9 +1015,9 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
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continue
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# wires
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portmap = db[y, x].bels[name].portmap
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tt.create_wire(portmap['I'], "IO_I")
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tt.create_wire(portmap['O'], "IO_O")
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tt.create_wire(portmap['OE'], "IO_OE")
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create_reuse_wire(tt, portmap['I'], "IO_I")
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create_reuse_wire(tt, portmap['O'], "IO_O")
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create_reuse_wire(tt, portmap['OE'], "IO_OE")
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# bels
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io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
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if simple_io and chip.name in {'GW1N-1'}:
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@ -1044,14 +1026,13 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
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tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)
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tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
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if 'ADCEN' in portmap:
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tt.create_wire(portmap['ADCEN'], "IO_ADCEN")
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create_reuse_wire(tt, portmap['ADCEN'], "IO_ADCEN")
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tt.add_bel_pin(io, "ADCEN", portmap['ADCEN'], PinType.INPUT)
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# bottom io
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if 'BOTTOM_IO_PORT_A' in portmap and portmap['BOTTOM_IO_PORT_A']:
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if not tt.has_wire(portmap['BOTTOM_IO_PORT_A']):
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tt.create_wire(portmap['BOTTOM_IO_PORT_A'], "IO_I")
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tt.create_wire(portmap['BOTTOM_IO_PORT_B'], "IO_I")
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create_reuse_wire(tt, portmap['BOTTOM_IO_PORT_A'], "IO_I")
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create_reuse_wire(tt, portmap['BOTTOM_IO_PORT_B'], "IO_I")
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tt.add_bel_pin(io, "BOTTOM_IO_PORT_A", portmap['BOTTOM_IO_PORT_A'], PinType.INPUT)
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tt.add_bel_pin(io, "BOTTOM_IO_PORT_B", portmap['BOTTOM_IO_PORT_B'], PinType.INPUT)
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# create IOLOGIC bels if any
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@ -1063,11 +1044,10 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
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for port, wire in db[y, x].bels[name].portmap.items():
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if port == 'FCLK': # XXX compatibility
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wire = f'FCLK{name[-1]}'
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if not tt.has_wire(wire):
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if port in {'CLK', 'PCLK', 'MCLK'}:
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tt.create_wire(wire, "TILE_CLK")
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else:
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tt.create_wire(wire, "IOL_PORT")
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if port in {'CLK', 'PCLK', 'MCLK'}:
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create_reuse_wire(tt, wire, "TILE_CLK")
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else:
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create_reuse_wire(tt, wire, "")
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if port in {'Q', 'Q0', 'Q1', 'Q2', 'Q3', 'Q4', 'Q5', 'Q6', 'Q7', 'Q8', 'Q9', 'DF', 'LAG', 'LEAD'}:
|
||||
tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
|
||||
else:
|
||||
|
|
@ -1088,28 +1068,28 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
|
|||
# setup LUT wires
|
||||
for i in range(8):
|
||||
for inp_name in lut_inputs:
|
||||
tt.create_wire(f"{inp_name}{i}", "LUT_IN")
|
||||
tt.create_wire(f"F{i}", "LUT_OUT")
|
||||
create_reuse_wire(tt, f"{inp_name}{i}", "LUT_IN")
|
||||
create_reuse_wire(tt, f"F{i}", "LUT_OUT")
|
||||
# experimental. the wire is false - it is assumed that DFF is always
|
||||
# connected to the LUT's output F{i}, but we can place primitives
|
||||
# arbitrarily and create a pass-through LUT afterwards.
|
||||
# just out of curiosity
|
||||
tt.create_wire(f"XD{i}", "FF_INPUT")
|
||||
tt.create_wire(f"Q{i}", "FF_OUT")
|
||||
create_reuse_wire(tt, f"XD{i}", "FF_INPUT")
|
||||
create_reuse_wire(tt, f"Q{i}", "FF_OUT")
|
||||
# setup DFF wires
|
||||
for j in range(3):
|
||||
tt.create_wire(f"CLK{j}", "TILE_CLK")
|
||||
tt.create_wire(f"LSR{j}", "TILE_LSR")
|
||||
tt.create_wire(f"CE{j}", "TILE_CE")
|
||||
create_reuse_wire(tt, f"CLK{j}", "TILE_CLK")
|
||||
create_reuse_wire(tt, f"LSR{j}", "TILE_LSR")
|
||||
create_reuse_wire(tt, f"CE{j}", "TILE_CE")
|
||||
# setup MUX2 wires
|
||||
for j in range(8):
|
||||
tt.create_wire(f"OF{j}", "MUX_OUT")
|
||||
tt.create_wire(f"SEL{j}", "MUX_SEL")
|
||||
tt.create_wire("OF30", "MUX_OUT")
|
||||
create_reuse_wire(tt, f"OF{j}", "MUX_OUT")
|
||||
create_reuse_wire(tt, f"SEL{j}", "MUX_SEL")
|
||||
create_reuse_wire(tt, "OF30", "MUX_OUT")
|
||||
# setup ALU wires
|
||||
for j in range(6):
|
||||
tt.create_wire(f"CIN{j}", "ALU_CIN")
|
||||
tt.create_wire(f"COUT{j}", "ALU_COUT")
|
||||
create_reuse_wire(tt, f"CIN{j}", "ALU_CIN")
|
||||
create_reuse_wire(tt, f"COUT{j}", "ALU_COUT")
|
||||
|
||||
# create logic cells
|
||||
for i in range(8):
|
||||
|
|
@ -1562,10 +1542,10 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
|
|||
pll.flags = BEL_FLAG_GLOBAL
|
||||
for pin, wire in portmap.items():
|
||||
if pin in pll_outputs:
|
||||
tt.create_wire(wire, "PLL_O")
|
||||
create_reuse_wire(tt, wire, "PLL_O")
|
||||
tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
|
||||
else:
|
||||
tt.create_wire(wire, "PLL_I")
|
||||
create_reuse_wire(tt, wire, "PLL_I")
|
||||
tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
|
||||
tdesc.tiletype = tiletype
|
||||
return tt
|
||||
|
|
|
|||
Loading…
Reference in New Issue