mirror of https://github.com/YosysHQ/nextpnr.git
871 lines
36 KiB
C++
871 lines
36 KiB
C++
#include "design_utils.h"
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#include "log.h"
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#include "nextpnr.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include "gowin.h"
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#include "gowin_utils.h"
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#include "pack.h"
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#include <cinttypes>
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NEXTPNR_NAMESPACE_BEGIN
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// ===================================
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// IO
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// ===================================
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// create IOB connections for gowin_pack
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// can be called repeatedly when switching inputs, disabled outputs do not change
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void GowinPacker::make_iob_nets(CellInfo &iob)
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{
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for (const auto &port : iob.ports) {
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const NetInfo *net = iob.getPort(port.first);
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std::string connected_net = "NET";
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if (net != nullptr) {
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if (ctx->verbose) {
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log_info("%s: %s - %s\n", ctx->nameOf(&iob), port.first.c_str(ctx), ctx->nameOf(net));
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}
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if (net->name == ctx->id("$PACKER_VCC")) {
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connected_net = "VCC";
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} else if (net->name == ctx->id("$PACKER_GND")) {
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connected_net = "GND";
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}
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iob.setParam(ctx->idf("NET_%s", port.first.c_str(ctx)), connected_net);
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}
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}
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}
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void GowinPacker::config_simple_io(CellInfo &ci)
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{
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if (ci.type.in(id_TBUF, id_IOBUF)) {
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return;
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}
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log_info("simple:%s\n", ctx->nameOf(&ci));
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ci.addInput(id_OEN);
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if (ci.type == id_OBUF) {
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ci.connectPort(id_OEN, ctx->nets.at(ctx->id("$PACKER_GND")).get());
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} else {
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NPNR_ASSERT(ci.type == id_IBUF);
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ci.connectPort(id_OEN, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
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}
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}
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void GowinPacker::config_bottom_row(CellInfo &ci, Loc loc, uint8_t cnd)
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{
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if (!gwu.has_bottom_io_cnds()) {
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return;
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}
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if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
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return;
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}
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if (loc.z != BelZ::IOBA_Z) {
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return;
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}
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auto connect_io_wire = [&](IdString port, IdString net_name) {
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// XXX it is very convenient that nothing terrible happens in case
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// of absence/presence of a port
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ci.disconnectPort(port);
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ci.addInput(port);
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if (net_name == id_VSS) {
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ci.connectPort(port, ctx->nets.at(ctx->id("$PACKER_GND")).get());
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} else {
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NPNR_ASSERT(net_name == id_VCC);
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ci.connectPort(port, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
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}
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};
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IdString wire_a_net = gwu.get_bottom_io_wire_a_net(cnd);
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connect_io_wire(id_BOTTOM_IO_PORT_A, wire_a_net);
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IdString wire_b_net = gwu.get_bottom_io_wire_b_net(cnd);
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connect_io_wire(id_BOTTOM_IO_PORT_B, wire_b_net);
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}
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// Attributes of deleted cells are copied
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void GowinPacker::trim_nextpnr_iobs(void)
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{
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_IBUF, id_I),
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CellTypePort(id_OBUF, id_O),
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CellTypePort(id_TBUF, id_O),
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CellTypePort(id_IOBUF, id_IO),
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};
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std::vector<IdString> to_remove;
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for (auto &cell : ctx->cells) {
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auto &ci = *cell.second;
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if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
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continue;
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NetInfo *i = ci.getPort(id_I);
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if (i && i->driver.cell) {
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if (!top_ports.count(CellTypePort(i->driver)))
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log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
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ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
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for (const auto &attr : ci.attrs) {
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i->driver.cell->setAttr(attr.first, attr.second);
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}
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}
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NetInfo *o = ci.getPort(id_O);
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if (o) {
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for (auto &usr : o->users) {
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if (!top_ports.count(CellTypePort(usr)))
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log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
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ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
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for (const auto &attr : ci.attrs) {
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usr.cell->setAttr(attr.first, attr.second);
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}
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// network/port attributes that can be set in the
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// restriction file and that need to be transferred to real
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// networks before nextpnr buffers are removed.
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NetInfo *dst_net = usr.cell->getPort(id_O);
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if (dst_net != nullptr) {
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for (const auto &attr : o->attrs) {
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if (!attr.first.in(id_CLOCK)) {
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continue;
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}
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dst_net->attrs[attr.first] = attr.second;
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}
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}
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}
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}
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NetInfo *io = ci.getPort(id_IO);
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if (io && io->driver.cell) {
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if (!top_ports.count(CellTypePort(io->driver)))
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log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
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ctx->nameOf(io->driver.cell), ctx->nameOf(io->driver.port));
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for (const auto &attr : ci.attrs) {
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io->driver.cell->setAttr(attr.first, attr.second);
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}
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}
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ci.disconnectPort(id_I);
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ci.disconnectPort(id_O);
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ci.disconnectPort(id_IO);
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to_remove.push_back(ci.name);
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}
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for (IdString cell_name : to_remove)
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ctx->cells.erase(cell_name);
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}
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BelId GowinPacker::bind_io(CellInfo &ci)
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{
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BelId bel = ctx->getBelByNameStr(ci.attrs.at(id_BEL).as_string());
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if (bel == BelId()) {
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log_error("No bel named %s\n", ci.attrs.at(id_BEL).as_string().c_str());
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}
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if (!ctx->checkBelAvail(bel)) {
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log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
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ctx->nameOf(ctx->getBoundBelCell(bel)));
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}
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ci.unsetAttr(id_BEL);
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ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
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return bel;
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}
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void GowinPacker::pack_iobs(void)
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{
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log_info("Pack IOBs...\n");
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trim_nextpnr_iobs();
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std::vector<IdString> cells_to_remove;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!is_io(&ci)) {
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continue;
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}
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// Special case of OBUF without input - we delete such things.
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if (ci.type == id_OBUF && !ci.getPort(id_I)) {
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ci.disconnectPort(id_O);
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cells_to_remove.push_back(ci.name);
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continue;
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}
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if (ci.attrs.count(id_BEL) == 0) {
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log_error("Unconstrained IO:%s\n", ctx->nameOf(&ci));
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}
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BelId io_bel = bind_io(ci);
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Loc io_loc = ctx->getBelLocation(io_bel);
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if (io_loc.y == ctx->getGridDimY() - 1) {
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config_bottom_row(ci, io_loc);
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}
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if (gwu.is_simple_io_bel(io_bel)) {
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config_simple_io(ci);
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}
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make_iob_nets(ci);
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}
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for (auto cell : cells_to_remove) {
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ctx->cells.erase(cell);
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}
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}
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// ===================================
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// Differential IO
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// ===================================
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std::pair<CellInfo *, CellInfo *> GowinPacker::get_pn_cells(const CellInfo &ci)
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{
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CellInfo *p, *n;
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switch (ci.type.hash()) {
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case ID_ELVDS_TBUF: /* fall-through */
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case ID_TLVDS_TBUF: /* fall-through */
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case ID_ELVDS_OBUF: /* fall-through */
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case ID_TLVDS_OBUF:
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p = net_only_drives(ctx, ci.ports.at(id_O).net, is_iob, id_I, true);
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n = net_only_drives(ctx, ci.ports.at(id_OB).net, is_iob, id_I, true);
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break;
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case ID_TLVDS_IBUF_ADC: /* fall-through */
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case ID_ELVDS_IBUF: /* fall-through */
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case ID_TLVDS_IBUF:
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p = net_driven_by(ctx, ci.ports.at(id_I).net, is_iob, id_O);
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n = net_driven_by(ctx, ci.ports.at(id_IB).net, is_iob, id_O);
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break;
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case ID_ELVDS_IOBUF: /* fall-through */
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case ID_TLVDS_IOBUF:
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p = net_only_drives(ctx, ci.ports.at(id_IO).net, is_iob, id_I);
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n = net_only_drives(ctx, ci.ports.at(id_IOB).net, is_iob, id_I);
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break;
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default:
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log_error("Bad diff IO '%s' type '%s'\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
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}
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return std::make_pair(p, n);
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}
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void GowinPacker::mark_iobs_as_diff(CellInfo &ci, std::pair<CellInfo *, CellInfo *> &pn_cells)
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{
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pn_cells.first->setParam(id_DIFF, std::string("P"));
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pn_cells.first->setParam(id_DIFF_TYPE, ci.type.str(ctx));
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pn_cells.second->setParam(id_DIFF, std::string("N"));
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pn_cells.second->setParam(id_DIFF_TYPE, ci.type.str(ctx));
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if (ci.params.count(id_ADC_IO)) {
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pn_cells.first->setParam(id_ADC_IO, ci.params.at(id_ADC_IO));
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pn_cells.second->setParam(id_ADC_IO, ci.params.at(id_ADC_IO));
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}
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}
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void GowinPacker::switch_diff_ports(CellInfo &ci, std::pair<CellInfo *, CellInfo *> &pn_cells,
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std::vector<IdString> &nets_to_remove)
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{
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CellInfo *iob_p = pn_cells.first;
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CellInfo *iob_n = pn_cells.second;
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if (ci.type.in(id_TLVDS_TBUF, id_TLVDS_OBUF, id_ELVDS_TBUF, id_ELVDS_OBUF)) {
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nets_to_remove.push_back(ci.getPort(id_O)->name);
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ci.disconnectPort(id_O);
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nets_to_remove.push_back(ci.getPort(id_OB)->name);
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ci.disconnectPort(id_OB);
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nets_to_remove.push_back(iob_n->getPort(id_I)->name);
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iob_n->disconnectPort(id_I);
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if (ci.type.in(id_TLVDS_TBUF, id_ELVDS_TBUF)) {
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NetInfo *oen_net = iob_n->getPort(id_OEN);
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if (oen_net != nullptr) {
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nets_to_remove.push_back(oen_net->name);
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}
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iob_n->disconnectPort(id_OEN);
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iob_p->disconnectPort(id_OEN);
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ci.movePortTo(id_OEN, iob_p, id_OEN);
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// MIPI
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if (ci.params.count(id_MIPI_OBUF)) {
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iob_p->setParam(id_MIPI_OBUF, 1);
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iob_n->setParam(id_MIPI_OBUF, 1);
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ci.movePortTo(id_IB, iob_n, id_I);
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iob_p->copyPortTo(id_OEN, iob_n, id_OEN);
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}
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}
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iob_p->disconnectPort(id_I);
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ci.movePortTo(id_I, iob_p, id_I);
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return;
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}
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if (ci.type.in(id_TLVDS_IBUF, id_ELVDS_IBUF)) {
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nets_to_remove.push_back(ci.getPort(id_I)->name);
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ci.disconnectPort(id_I);
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nets_to_remove.push_back(ci.getPort(id_IB)->name);
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ci.disconnectPort(id_IB);
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iob_n->disconnectPort(id_O);
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iob_p->disconnectPort(id_O);
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ci.movePortTo(id_O, iob_p, id_O);
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return;
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}
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if (ci.type.in(id_TLVDS_IOBUF, id_ELVDS_IOBUF)) {
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nets_to_remove.push_back(ci.getPort(id_IO)->name);
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ci.disconnectPort(id_IO);
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nets_to_remove.push_back(ci.getPort(id_IOB)->name);
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ci.disconnectPort(id_IOB);
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nets_to_remove.push_back(iob_n->getPort(id_I)->name);
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iob_n->disconnectPort(id_I);
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iob_n->disconnectPort(id_OEN);
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iob_p->disconnectPort(id_OEN);
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ci.movePortTo(id_OEN, iob_p, id_OEN);
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iob_p->disconnectPort(id_I);
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ci.movePortTo(id_I, iob_p, id_I);
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iob_p->disconnectPort(id_O);
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ci.movePortTo(id_O, iob_p, id_O);
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return;
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}
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if (ci.type.in(id_TLVDS_IBUF_ADC)) {
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nets_to_remove.push_back(ci.getPort(id_I)->name);
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ci.disconnectPort(id_I);
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nets_to_remove.push_back(ci.getPort(id_IB)->name);
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ci.disconnectPort(id_IB);
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iob_p->disconnectPort(id_O);
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iob_n->disconnectPort(id_O);
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ci.movePortTo(id_ADCEN, iob_p, id_ADCEN);
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return;
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}
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}
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// ===================================
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// I3C
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// ===================================
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void GowinPacker::pack_i3c(void)
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{
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log_info("Pack I3C IOs...\n");
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std::vector<IdString> cells_to_remove;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!is_i3c(&ci)) {
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continue;
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}
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// check for I3C-capable pin A
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CellInfo *iob = net_only_drives(ctx, ci.ports.at(id_IO).net, is_iob, id_I);
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if (iob == nullptr || iob->bel == BelId()) {
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log_error("I3C %s IO is not connected to the input pin or the pin is not constrained.\n", ctx->nameOf(&ci));
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}
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BelId iob_bel = iob->bel;
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Loc iob_loc = ctx->getBelLocation(iob_bel);
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if (!gwu.get_i3c_capable(iob_loc.x, iob_loc.y)) {
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log_error("Can't place %s. Not I3C capable X%dY%d.\n", ctx->nameOf(&ci), iob_loc.x, iob_loc.y);
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}
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ci.disconnectPort(id_IO);
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iob->disconnectPort(id_I);
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ci.movePortTo(id_I, iob, id_I);
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ci.movePortTo(id_O, iob, id_O);
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iob->disconnectPort(id_OEN);
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ci.movePortTo(id_MODESEL, iob, id_OEN);
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iob->setParam(id_I3C_IOBUF, 1);
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cells_to_remove.push_back(ci.name);
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}
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for (auto cell : cells_to_remove) {
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ctx->cells.erase(cell);
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}
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}
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// ===================================
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// MIPI IO
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// ===================================
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void GowinPacker::pack_mipi(void)
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{
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log_info("Pack MIPI IOs...\n");
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std::vector<std::unique_ptr<CellInfo>> new_cells;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!is_mipi(&ci)) {
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continue;
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}
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switch (ci.type.hash()) {
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case ID_MIPI_OBUF_A: /* fall-through */
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case ID_MIPI_OBUF: {
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// check for MIPI-capable pin
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CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(id_O).net, is_iob, id_I, true);
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if (out_iob == nullptr || out_iob->bel == BelId()) {
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log_error("MIPI %s is not connected to the output pin or the pin is not constrained.\n",
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ctx->nameOf(&ci));
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}
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if (out_iob->params.count(id_I3C_IOBUF)) {
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log_error("Can't place MIPI %s. Conflict with I3C %s.\n", ctx->nameOf(&ci), ctx->nameOf(out_iob));
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}
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BelId iob_bel = out_iob->bel;
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Loc iob_loc = ctx->getBelLocation(iob_bel);
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iob_loc.z = BelZ::MIPIOBUF_Z;
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BelId mipi_bel = ctx->getBelByLocation(iob_loc);
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if (mipi_bel == BelId()) {
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log_error("Can't place MIPI %s at X%dY%d/IOBA.\n", ctx->nameOf(&ci), iob_loc.x, iob_loc.y);
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}
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if (ci.type == id_MIPI_OBUF_A) {
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// if serialization is used then IL and input of serializator must be in the same network
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NetInfo *i_net = ci.getPort(id_I);
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NetInfo *il_net = ci.getPort(id_IL);
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if (i_net != il_net) {
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if (i_net != nullptr && is_iologico(i_net->driver.cell)) {
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if (i_net->driver.cell->getPort(id_D0) != ci.getPort(id_IL)) {
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log_error("MIPI %s port IL and IOLOGIC %s port D0 are in differrent networks!\n",
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ctx->nameOf(&ci), ctx->nameOf(i_net->driver.cell));
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}
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} else {
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log_error("MIPI %s ports IL and I are in differrent networks!\n", ctx->nameOf(&ci));
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}
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}
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ci.disconnectPort(id_IL);
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}
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ctx->bindBel(mipi_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
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// Create TBUF with additional input IB
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IdString mipi_tbuf_name = gwu.create_aux_name(ci.name);
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new_cells.push_back(gwu.create_cell(mipi_tbuf_name, id_TLVDS_TBUF));
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CellInfo *mipi_tbuf = new_cells.back().get();
|
|
mipi_tbuf->addInput(id_I);
|
|
mipi_tbuf->addInput(id_IB);
|
|
mipi_tbuf->addOutput(id_O);
|
|
mipi_tbuf->addOutput(id_OB);
|
|
mipi_tbuf->addInput(id_OEN);
|
|
ci.movePortTo(id_I, mipi_tbuf, id_I);
|
|
ci.movePortTo(id_IB, mipi_tbuf, id_IB);
|
|
ci.movePortTo(id_O, mipi_tbuf, id_O);
|
|
ci.movePortTo(id_OB, mipi_tbuf, id_OB);
|
|
ci.movePortTo(id_MODESEL, mipi_tbuf, id_OEN);
|
|
|
|
mipi_tbuf->setParam(id_MIPI_OBUF, 1);
|
|
} break;
|
|
case ID_MIPI_IBUF: {
|
|
// check for MIPI-capable pin A
|
|
CellInfo *in_iob = net_only_drives(ctx, ci.ports.at(id_IO).net, is_iob, id_I);
|
|
if (in_iob == nullptr || in_iob->bel == BelId()) {
|
|
log_error("MIPI %s IO is not connected to the input pin or the pin is not constrained.\n",
|
|
ctx->nameOf(&ci));
|
|
}
|
|
// check A IO placing
|
|
if (in_iob->params.count(id_I3C_IOBUF)) {
|
|
log_error("Can't place MIPI %s. Conflict with I3C %s.\n", ctx->nameOf(&ci), ctx->nameOf(in_iob));
|
|
}
|
|
BelId iob_bel = in_iob->bel;
|
|
Loc iob_loc = ctx->getBelLocation(iob_bel);
|
|
if (iob_loc.z != BelZ::IOBA_Z) {
|
|
log_error("MIPI %s IO pin must be connected to the A IO pin.\n", ctx->nameOf(&ci));
|
|
}
|
|
|
|
iob_loc.z = BelZ::MIPIIBUF_Z;
|
|
BelId mipi_bel = ctx->getBelByLocation(iob_loc);
|
|
if (mipi_bel == BelId()) {
|
|
log_error("Can't place MIPI %s at X%dY%d/IOBA.\n", ctx->nameOf(&ci), iob_loc.x, iob_loc.y);
|
|
}
|
|
|
|
// check for MIPI-capable pin B
|
|
CellInfo *inb_iob = net_only_drives(ctx, ci.ports.at(id_IOB).net, is_iob, id_I);
|
|
if (inb_iob == nullptr || inb_iob->bel == BelId()) {
|
|
log_error("MIPI %s IOB is not connected to the input pin or the pin is not constrained.\n",
|
|
ctx->nameOf(&ci));
|
|
}
|
|
// check B IO placing
|
|
if (inb_iob->params.count(id_I3C_IOBUF)) {
|
|
log_error("Can't place MIPI %s. Conflict with I3C %s.\n", ctx->nameOf(&ci), ctx->nameOf(inb_iob));
|
|
}
|
|
BelId iobb_bel = inb_iob->bel;
|
|
Loc iobb_loc = ctx->getBelLocation(iobb_bel);
|
|
if (iobb_loc.z != BelZ::IOBB_Z || iobb_loc.x != iob_loc.x || iobb_loc.y != iob_loc.y) {
|
|
log_error("MIPI %s IOB pin must be connected to the B IO pin.\n", ctx->nameOf(&ci));
|
|
}
|
|
// MIPI IBUF uses next pair of IOs too
|
|
Loc iob_next_loc(iob_loc);
|
|
++iob_next_loc.x;
|
|
iob_next_loc.z = BelZ::IOBA_Z;
|
|
CellInfo *inc_iob = ctx->getBoundBelCell(ctx->getBelByLocation(iob_next_loc));
|
|
iob_next_loc.z = BelZ::IOBB_Z;
|
|
CellInfo *other_cell_b = ctx->getBoundBelCell(ctx->getBelByLocation(iob_next_loc));
|
|
if (inc_iob != nullptr || other_cell_b != nullptr) {
|
|
log_error("MIPI %s cannot be placed in same IO with %s.\n", ctx->nameOf(&ci),
|
|
inc_iob == nullptr ? ctx->nameOf(other_cell_b) : ctx->nameOf(inc_iob));
|
|
}
|
|
|
|
ctx->bindBel(mipi_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
|
|
|
|
// reconnect wires
|
|
// A
|
|
ci.disconnectPort(id_IO);
|
|
in_iob->disconnectPort(id_I);
|
|
ci.movePortTo(id_I, in_iob, id_I);
|
|
ci.movePortTo(id_OH, in_iob, id_O);
|
|
in_iob->disconnectPort(id_OEN);
|
|
ci.movePortTo(id_OEN, in_iob, id_OEN);
|
|
// B
|
|
ci.disconnectPort(id_IO);
|
|
inb_iob->disconnectPort(id_I);
|
|
ci.movePortTo(id_IB, inb_iob, id_I);
|
|
ci.movePortTo(id_OB, inb_iob, id_O);
|
|
inb_iob->disconnectPort(id_OEN);
|
|
ci.movePortTo(id_OENB, inb_iob, id_OEN);
|
|
// MIPI enable (?)
|
|
ci.addInput(ctx->id("MIPIEN0"));
|
|
ci.connectPort(ctx->id("MIPIEN0"), ctx->nets.at(ctx->id("$PACKER_GND")).get());
|
|
ci.addInput(ctx->id("MIPIEN1"));
|
|
ci.connectPort(ctx->id("MIPIEN1"), ctx->nets.at(ctx->id("$PACKER_VCC")).get());
|
|
|
|
in_iob->setParam(id_MIPI_IBUF, 1);
|
|
inb_iob->setParam(id_MIPI_IBUF, 1);
|
|
} break;
|
|
default:
|
|
log_error("MIPI %s is not implemented.\n", ci.type.c_str(ctx));
|
|
}
|
|
}
|
|
for (auto &ncell : new_cells) {
|
|
ctx->cells[ncell->name] = std::move(ncell);
|
|
}
|
|
}
|
|
|
|
void GowinPacker::pack_diff_iobs(void)
|
|
{
|
|
log_info("Pack diff IOBs...\n");
|
|
std::vector<IdString> cells_to_remove, nets_to_remove;
|
|
|
|
for (auto &cell : ctx->cells) {
|
|
CellInfo &ci = *cell.second;
|
|
if (!is_diffio(&ci)) {
|
|
continue;
|
|
}
|
|
if (!gwu.is_diff_io_supported(ci.type)) {
|
|
log_error("%s is not supported\n", ci.type.c_str(ctx));
|
|
}
|
|
cells_to_remove.push_back(ci.name);
|
|
auto pn_cells = get_pn_cells(ci);
|
|
NPNR_ASSERT(pn_cells.first != nullptr && pn_cells.second != nullptr);
|
|
|
|
mark_iobs_as_diff(ci, pn_cells);
|
|
switch_diff_ports(ci, pn_cells, nets_to_remove);
|
|
}
|
|
|
|
for (auto cell : cells_to_remove) {
|
|
ctx->cells.erase(cell);
|
|
}
|
|
for (auto net : nets_to_remove) {
|
|
ctx->nets.erase(net);
|
|
}
|
|
}
|
|
|
|
static bool is_ff(const Context *ctx, CellInfo *cell) { return is_dff(cell); }
|
|
|
|
static bool incompatible_ffs(IdString type_a, IdString type_b)
|
|
{
|
|
return type_a != type_b &&
|
|
((type_a == id_DFFS && type_b != id_DFFR) || (type_a == id_DFFR && type_b != id_DFFS) ||
|
|
(type_a == id_DFFSE && type_b != id_DFFRE) || (type_a == id_DFFRE && type_b != id_DFFSE) ||
|
|
(type_a == id_DFFP && type_b != id_DFFC) || (type_a == id_DFFC && type_b != id_DFFP) ||
|
|
(type_a == id_DFFPE && type_b != id_DFFCE) || (type_a == id_DFFCE && type_b != id_DFFPE) ||
|
|
(type_a == id_DFFNS && type_b != id_DFFNR) || (type_a == id_DFFNR && type_b != id_DFFNS) ||
|
|
(type_a == id_DFFNSE && type_b != id_DFFNRE) || (type_a == id_DFFNRE && type_b != id_DFFNSE) ||
|
|
(type_a == id_DFFNP && type_b != id_DFFNC) || (type_a == id_DFFNC && type_b != id_DFFNP) ||
|
|
(type_a == id_DFFNPE && type_b != id_DFFNCE) || (type_a == id_DFFNCE && type_b != id_DFFNPE) ||
|
|
(type_a == id_DFF && type_b != id_DFF) || (type_a == id_DFFN && type_b != id_DFFN) ||
|
|
(type_a == id_DFFE && type_b != id_DFFE) || (type_a == id_DFFNE && type_b != id_DFFNE));
|
|
}
|
|
|
|
void GowinPacker::pack_io_regs(void)
|
|
{
|
|
log_info("Pack FFs into IO cells...\n");
|
|
std::vector<IdString> cells_to_remove;
|
|
std::vector<IdString> nets_to_remove;
|
|
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
|
|
|
for (auto &cell : ctx->cells) {
|
|
CellInfo &ci = *cell.second;
|
|
if (!is_io(&ci)) {
|
|
continue;
|
|
}
|
|
if (ci.attrs.count(id_NOIOBFF)) {
|
|
if (ctx->debug) {
|
|
log_info(" NOIOBFF attribute at %s. Skipping FF placement.\n", ctx->nameOf(&ci));
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// In the case of placing multiple registers in the IO it should be
|
|
// noted that the CLK, ClockEnable and LocalSetReset nets must
|
|
// match.
|
|
const NetInfo *clk_net = nullptr;
|
|
const NetInfo *ce_net = nullptr;
|
|
const NetInfo *lsr_net = nullptr;
|
|
IdString reg_type;
|
|
|
|
// input reg in IO
|
|
CellInfo *iologic_i = nullptr;
|
|
if ((ci.type == id_IBUF && (ctx->settings.count(id_IREG_IN_IOB) || ci.attrs.count(id_IOBFF))) ||
|
|
(ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF)))) {
|
|
|
|
if (ci.getPort(id_O) == nullptr) {
|
|
continue;
|
|
}
|
|
// OBUF O -> D FF
|
|
CellInfo *ff = net_only_drives(ctx, ci.ports.at(id_O).net, is_ff, id_D);
|
|
if (ff == nullptr) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Port O of %s is not connected to FF.\n", ctx->nameOf(&ci));
|
|
}
|
|
continue;
|
|
}
|
|
if (ci.ports.at(id_O).net->users.entries() != 1) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Port O of %s is the driver of %s multi-sink network.\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(ci.ports.at(id_O).net));
|
|
}
|
|
continue;
|
|
}
|
|
BelId l_bel = get_iologici_bel(&ci);
|
|
if (l_bel == BelId()) {
|
|
continue;
|
|
}
|
|
if (ctx->debug) {
|
|
log_info(" trying %s ff as Input Register of %s IO\n", ctx->nameOf(ff), ctx->nameOf(&ci));
|
|
}
|
|
|
|
clk_net = ff->getPort(id_CLK);
|
|
ce_net = ff->getPort(id_CE);
|
|
for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
|
|
lsr_net = ff->getPort(port);
|
|
if (lsr_net != nullptr) {
|
|
break;
|
|
}
|
|
}
|
|
reg_type = ff->type;
|
|
|
|
// create IOLOGIC cell for flipflop
|
|
IdString iologic_name = gwu.create_aux_name(ci.name, 0, "_iobff$");
|
|
auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICI_EMPTY);
|
|
new_cells.push_back(std::move(iologic_cell));
|
|
iologic_i = new_cells.back().get();
|
|
|
|
// move ports
|
|
for (auto &port : ff->ports) {
|
|
IdString port_name = port.first;
|
|
ff->movePortTo(port_name, iologic_i, port_name != id_Q ? port_name : id_Q4);
|
|
}
|
|
if (ctx->verbose) {
|
|
log_info(" place FF %s into IBUF %s, make iologic_i %s\n", ctx->nameOf(ff), ctx->nameOf(&ci),
|
|
ctx->nameOf(iologic_i));
|
|
}
|
|
iologic_i->setAttr(id_HAS_REG, 1);
|
|
iologic_i->setAttr(id_IREG_TYPE, ff->type.str(ctx));
|
|
cells_to_remove.push_back(ff->name);
|
|
}
|
|
|
|
// output reg in IO
|
|
CellInfo *iologic_o = nullptr;
|
|
if ((ci.type == id_OBUF && (ctx->settings.count(id_OREG_IN_IOB) || ci.attrs.count(id_IOBFF))) ||
|
|
(ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF)))) {
|
|
do {
|
|
if (ci.getPort(id_I) == nullptr) {
|
|
break;
|
|
}
|
|
// OBUF I <- Q FF
|
|
CellInfo *ff = net_driven_by(ctx, ci.ports.at(id_I).net, is_ff, id_Q);
|
|
if (ff == nullptr) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Port I of %s is not connected to FF.\n", ctx->nameOf(&ci));
|
|
}
|
|
} else {
|
|
if (ci.ports.at(id_I).net->users.entries() != 1) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Port I of %s is not the only sink on the %s network.\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(ci.ports.at(id_I).net));
|
|
}
|
|
break;
|
|
}
|
|
BelId l_bel = get_iologico_bel(&ci);
|
|
if (l_bel == BelId()) {
|
|
break;
|
|
}
|
|
|
|
const NetInfo *this_clk_net = ff->getPort(id_CLK);
|
|
const NetInfo *this_ce_net = ff->getPort(id_CE);
|
|
const NetInfo *this_lsr_net;
|
|
for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
|
|
this_lsr_net = ff->getPort(port);
|
|
if (this_lsr_net != nullptr) {
|
|
break;
|
|
}
|
|
}
|
|
// The IOBUF may already have registers placed
|
|
if (ci.type == id_IOBUF) {
|
|
if (iologic_i != nullptr) {
|
|
if (incompatible_ffs(ff->type, reg_type)) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("OREG type conflict:%s:%s vs %s IREG:%s\n", ctx->nameOf(ff),
|
|
ff->type.c_str(ctx), ctx->nameOf(&ci), reg_type.c_str(ctx));
|
|
}
|
|
break;
|
|
} else {
|
|
if (clk_net != this_clk_net || ce_net != this_ce_net || lsr_net != this_lsr_net) {
|
|
if (clk_net != this_clk_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting OREG CLK nets at %s:'%s' vs '%s'\n",
|
|
ctx->nameOf(&ci), ctx->nameOf(clk_net),
|
|
ctx->nameOf(this_clk_net));
|
|
}
|
|
}
|
|
if (ce_net != this_ce_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting OREG CE nets at %s:'%s' vs '%s'\n",
|
|
ctx->nameOf(&ci), ctx->nameOf(ce_net),
|
|
ctx->nameOf(this_ce_net));
|
|
}
|
|
}
|
|
if (lsr_net != this_lsr_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting OREG LSR nets at %s:'%s' vs '%s'\n",
|
|
ctx->nameOf(&ci), ctx->nameOf(lsr_net),
|
|
ctx->nameOf(this_lsr_net));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
clk_net = this_clk_net;
|
|
ce_net = this_ce_net;
|
|
lsr_net = this_lsr_net;
|
|
reg_type = ff->type;
|
|
}
|
|
}
|
|
|
|
// create IOLOGIC cell for flipflop
|
|
IdString iologic_name = gwu.create_aux_name(ci.name, 1, "_iobff$");
|
|
auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICO_EMPTY);
|
|
new_cells.push_back(std::move(iologic_cell));
|
|
iologic_o = new_cells.back().get();
|
|
|
|
// move ports
|
|
for (auto &port : ff->ports) {
|
|
IdString port_name = port.first;
|
|
ff->movePortTo(port_name, iologic_o, port_name != id_D ? port_name : id_D0);
|
|
}
|
|
if (ctx->verbose) {
|
|
log_info(" place FF %s into OBUF %s, make iologic_o %s\n", ctx->nameOf(ff), ctx->nameOf(&ci),
|
|
ctx->nameOf(iologic_o));
|
|
}
|
|
iologic_o->setAttr(id_HAS_REG, 1);
|
|
iologic_o->setAttr(id_OREG_TYPE, ff->type.str(ctx));
|
|
cells_to_remove.push_back(ff->name);
|
|
}
|
|
} while (false);
|
|
}
|
|
|
|
// output enable reg in IO
|
|
if (ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF))) {
|
|
do {
|
|
if (ci.getPort(id_OEN) == nullptr) {
|
|
break;
|
|
}
|
|
// IOBUF OEN <- Q FF
|
|
CellInfo *ff = net_driven_by(ctx, ci.ports.at(id_OEN).net, is_ff, id_Q);
|
|
if (ff != nullptr) {
|
|
if (ci.ports.at(id_OEN).net->users.entries() != 1) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Port OEN of %s is not the only sink on the %s network.\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(ci.ports.at(id_OEN).net));
|
|
}
|
|
break;
|
|
}
|
|
BelId l_bel = get_iologico_bel(&ci);
|
|
if (l_bel == BelId()) {
|
|
break;
|
|
}
|
|
if (ctx->debug) {
|
|
log_info(" trying %s ff as Output Enable Register of %s IO\n", ctx->nameOf(ff),
|
|
ctx->nameOf(&ci));
|
|
}
|
|
|
|
const NetInfo *this_clk_net = ff->getPort(id_CLK);
|
|
const NetInfo *this_ce_net = ff->getPort(id_CE);
|
|
const NetInfo *this_lsr_net;
|
|
for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
|
|
this_lsr_net = ff->getPort(port);
|
|
if (this_lsr_net != nullptr) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
// The IOBUF may already have registers placed
|
|
if (iologic_i != nullptr || iologic_o != nullptr) {
|
|
if (iologic_o == nullptr) {
|
|
iologic_o = iologic_i;
|
|
}
|
|
if (incompatible_ffs(ff->type, reg_type)) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("TREG type conflict:%s:%s vs %s IREG/OREG:%s\n", ctx->nameOf(ff),
|
|
ff->type.c_str(ctx), ctx->nameOf(&ci), reg_type.c_str(ctx));
|
|
}
|
|
break;
|
|
} else {
|
|
if (clk_net != this_clk_net || ce_net != this_ce_net || lsr_net != this_lsr_net) {
|
|
if (clk_net != this_clk_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting TREG CLK nets at %s:'%s' vs '%s'\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(clk_net), ctx->nameOf(this_clk_net));
|
|
}
|
|
}
|
|
if (ce_net != this_ce_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting TREG CE nets at %s:'%s' vs '%s'\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(ce_net), ctx->nameOf(this_ce_net));
|
|
}
|
|
}
|
|
if (lsr_net != this_lsr_net) {
|
|
if (ci.attrs.count(id_IOBFF)) {
|
|
log_warning("Conflicting TREG LSR nets at %s:'%s' vs '%s'\n", ctx->nameOf(&ci),
|
|
ctx->nameOf(lsr_net), ctx->nameOf(this_lsr_net));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (iologic_o == nullptr) {
|
|
// create IOLOGIC cell for flipflop
|
|
IdString iologic_name = gwu.create_aux_name(ci.name, 2, "_iobff$");
|
|
auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICO_EMPTY);
|
|
new_cells.push_back(std::move(iologic_cell));
|
|
iologic_o = new_cells.back().get();
|
|
}
|
|
|
|
// move ports
|
|
for (auto &port : ff->ports) {
|
|
IdString port_name = port.first;
|
|
if (port_name == id_Q) {
|
|
continue;
|
|
}
|
|
ff->movePortTo(port_name, iologic_o, port_name != id_D ? port_name : id_TX);
|
|
}
|
|
|
|
nets_to_remove.push_back(ci.getPort(id_OEN)->name);
|
|
ci.disconnectPort(id_OEN);
|
|
ff->disconnectPort(id_Q);
|
|
|
|
if (ctx->verbose) {
|
|
log_info(" place FF %s into IOBUF %s, make iologic_o %s\n", ctx->nameOf(ff), ctx->nameOf(&ci),
|
|
ctx->nameOf(iologic_o));
|
|
}
|
|
iologic_o->setAttr(id_HAS_REG, 1);
|
|
iologic_o->setAttr(id_TREG_TYPE, ff->type.str(ctx));
|
|
cells_to_remove.push_back(ff->name);
|
|
}
|
|
} while (false);
|
|
}
|
|
}
|
|
|
|
for (auto cell : cells_to_remove) {
|
|
ctx->cells.erase(cell);
|
|
}
|
|
|
|
for (auto &ncell : new_cells) {
|
|
ctx->cells[ncell->name] = std::move(ncell);
|
|
}
|
|
|
|
for (auto net : nets_to_remove) {
|
|
ctx->nets.erase(net);
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|