nextpnr/himbaechel/uarch/gowin
YRabbit 764c6a6696
Gowin. Implement CLKDIV. (#1691)
Add CLKDIV — a frequency divider with ratios of 1, 2, 3, 3.5, 4,
5, 6, 7, and 8.

A direct, non-switchable connection to CLKDIV2 makes placement more
difficult — we have to account for CLKDIV2’s occupancy for IOLOGIC and,
if necessary, duplicate the cell, as well as create clusters of CLKDIV
and CLKDIV2.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-04-06 15:34:34 +02:00
..
CMakeLists.txt Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
constids.inc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
cst.cc Gowin. Ignore empty lines. (#1626) 2026-01-20 08:11:48 +01:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc Gowin. Add GW5AST-138C chip. (#1631) 2026-01-31 13:01:22 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin.cc Gowin. Implement CLKDIV. (#1691) 2026-04-06 15:34:34 +02:00
gowin.h Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
gowin_arch_gen.py Gowin. Implement CLKDIV. (#1691) 2026-04-06 15:34:34 +02:00
gowin_utils.cc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
gowin_utils.h Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
pack.cc Gowin. Implement CLKDIV. (#1691) 2026-04-06 15:34:34 +02:00
pack.h gowin: add DL-series latch cell support (#1652) 2026-03-14 19:12:08 +00:00
pack_bsram.cc GOWIN. BUGFIX. BSRAM port renaming. (#1669) 2026-03-14 20:52:05 +00:00
pack_dsp.cc Gowin. DSP. Refactor port renaming. 2026-03-04 09:04:55 +01:00
pack_io.cc Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
pack_iologic.cc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
pack_luts.cc clangformat 2026-03-24 19:06:31 +01:00