remove debug

himbaechel/uarch/gatemate/gatemate.cc

@@ -308,6 +308,7 @@ void GateMateImpl::postPlace()
     repack();
     ctx->assignArchInfo();
     used_cpes.resize(ctx->getGridDimX() * ctx->getGridDimY());
+    block_perm.resize(ctx->getGridDimX() * ctx->getGridDimY());
     for (auto &cell : ctx->cells) {
         // We need to skip CPE_MULT since using CP outputs is mandatory
         // even if output is actually not connected
@@ -317,14 +318,18 @@ void GateMateImpl::postPlace()
             marked_used = true;
         if (marked_used)
             used_cpes[cell.second.get()->bel.tile] = true;
+        if (cell.second.get()->type.in(id_CPE_MX4, id_CPE_MULT))
+            block_perm[cell.second.get()->bel.tile] = true;
     }
 }
 bool GateMateImpl::checkPipAvail(PipId pip) const
 {
     const auto &extra_data = *pip_extra_data(pip);
-    if (extra_data.type != PipExtra::PIP_EXTRA_MUX || (extra_data.flags & MUX_ROUTING) == 0)
+    if (extra_data.type != PipExtra::PIP_EXTRA_MUX || (extra_data.flags & (MUX_ROUTING | MUX_PERMUTATION)) == 0)
         return true;
-    if (used_cpes[pip.tile])
+    if ((extra_data.flags & MUX_ROUTING) && used_cpes[pip.tile])
+        return false;
+    if ((extra_data.flags & MUX_PERMUTATION) && (extra_data.value!=0) && block_perm[pip.tile])
         return false;
     return true;
 }

himbaechel/uarch/gatemate/gatemate.h

@@ -97,6 +97,7 @@ struct GateMateImpl : HimbaechelAPI
     pool<IdString> multiplier_zero_drivers;
     std::vector<CellInfo *> multipliers;
     std::vector<bool> used_cpes;
+    std::vector<bool> block_perm;
     int fpga_mode;
     int timing_mode;
     std::map<const NetInfo *, int> global_signals;

himbaechel/uarch/gatemate/pack.cc

@@ -309,16 +309,6 @@ void GateMatePacker::repack_cpe()
                 if (!cell.second->params.count(id_INIT_L20))
                     cell.second->params[id_INIT_L20] = Property(LUT_D1, 4);
             }
-            if (cell.second->getPort(id_IN1) && cell.second->getPort(id_IN2)) {
-                if (cell.second->getPort(id_IN1) == cell.second->getPort(id_IN2)) {
-                    log_error("Used same signal for IN1 and IN2 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
-            if (cell.second->getPort(id_IN3) && cell.second->getPort(id_IN4)) {
-                if (cell.second->getPort(id_IN3) == cell.second->getPort(id_IN4)) {
-                    log_error("Used same signal for IN3 and IN4 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
             cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1);
         } else if (cell.second->type.in(id_CPE_LT_L)) {
             BelId bel = cell.second->bel;
@@ -328,16 +318,6 @@ void GateMatePacker::repack_cpe()
             loc.z = CPE_LT_FULL_Z;
             ctx->unbindBel(bel);
             ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength);
-            if (cell.second->getPort(id_IN1) && cell.second->getPort(id_IN2)) {
-                if (cell.second->getPort(id_IN1) == cell.second->getPort(id_IN2)) {
-                    log_error("Used same signal for IN1 and IN2 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
-            if (cell.second->getPort(id_IN3) && cell.second->getPort(id_IN4)) {
-                if (cell.second->getPort(id_IN3) == cell.second->getPort(id_IN4)) {
-                    log_error("Used same signal for IN3 and IN4 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
             cell.second->renamePort(id_IN1, id_IN5);
             cell.second->renamePort(id_IN2, id_IN6);
             cell.second->renamePort(id_IN3, id_IN7);
@@ -394,18 +374,6 @@ void GateMatePacker::repack_cpe()
             upper->movePortTo(id_IN4, cell.second.get(), id_IN4);
             upper->movePortTo(id_OUT, cell.second.get(), id_OUT2);
             upper->movePortTo(id_CPOUT, cell.second.get(), id_CPOUT2);
-            if (cell.second->getPort(id_IN1) && cell.second->getPort(id_IN2)) {
-                if (cell.second->getPort(id_IN1) == cell.second->getPort(id_IN2)) {
-                    log_error("Used same signal for IN1 and IN2 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
-            if (cell.second->getPort(id_IN3) && cell.second->getPort(id_IN4)) {
-                if (cell.second->getPort(id_IN3) == cell.second->getPort(id_IN4)) {
-                    log_error("Used same signal for IN3 and IN4 in %s\n", cell.second->name.c_str(ctx));
-                }
-            }
-
-
         }
         // Mark for deletion
         else if (cell.second->type.in(id_CPE_LT_U, id_CPE_DUMMY)) {