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ice40: only set/clear negclk bit if IO clock actually used

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Signed-off-by: gatecat <[email protected]>
This commit is contained in:
gatecat
2023-09-08 09:15:27 +02:00
committed by myrtle
parent eef5243fba
commit f9825c3130
1 changed files with 2 additions and 1 deletions
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ice40/bitstream.cc
+2 -1
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@@ -540,7 +540,8 @@ void write_asc(const Context *ctx, std::ostream &out)
bool val = (pin_type >> i) & 0x01;
set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
}
set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
if (cell.second->getPort(id_INPUT_CLK) || cell.second->getPort(id_OUTPUT_CLK))
set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
bool input_en = false;
if ((ctx->wire_to_net[ctx->getBelPinWire(bel, id_D_IN_0).index] != nullptr) ||