From e6522266303b00865d3a225153a7c2daabff1c68 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 17 Mar 2026 10:34:59 +0000 Subject: [PATCH] xilinx: Prohibit IDELMUXE3 route throughs Signed-off-by: gatecat --- himbaechel/uarch/xilinx/gen/xilinx_gen.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/himbaechel/uarch/xilinx/gen/xilinx_gen.py b/himbaechel/uarch/xilinx/gen/xilinx_gen.py index 9ae8fa5b..1a18c1f4 100644 --- a/himbaechel/uarch/xilinx/gen/xilinx_gen.py +++ b/himbaechel/uarch/xilinx/gen/xilinx_gen.py @@ -228,7 +228,9 @@ def import_tiletype(ch: Chip, tile: xilinx_device.Tile): (bel_name == "BDI1MUX" and bel_pin == "DI") or \ (bel_name == "CDI1MUX" and bel_pin == "DI") or \ (bel_name.startswith("TFBUSED")) or \ - (bel_name == "OMUX"): + (bel_name == "OMUX") or \ + (bel_name == "IDELMUXE3"): + continue add_pip(lookup_site_wire(site_pip.src_wire()), lookup_site_wire(site_pip.dst_wire()),