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xilinx: Small tweak to delay prediction 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-08-11 15:03:04 +02:00
parent a435792828
commit df871def22
1 changed files with 5 additions and 1 deletions
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6
himbaechel/uarch/xilinx/xilinx.cc
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@ -775,8 +775,12 @@ delay_t XilinxImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel,
int sx, sy, dx, dy; int sx, sy, dx, dy;
tile_xy(ctx->chip_info, src_bel.tile, sx, sy); tile_xy(ctx->chip_info, src_bel.tile, sx, sy);
tile_xy(ctx->chip_info, dst_bel.tile, dx, dy); tile_xy(ctx->chip_info, dst_bel.tile, dx, dy);
if (dst_pin == id_CIN && src_pin == id_CO3)
return 0;
// TODO: improve sophistication here based on old nextpnr-xilinx code // TODO: improve sophistication here based on old nextpnr-xilinx code
return 500 + 25 * (2 * std::abs(dy - sy) + std::abs(dx - sx)); int dist_x = std::abs(dx - sx), dist_y = std::abs(dy - sy);
return 500 + 12 * (2 * std::max(dist_y - 6, 0) + 4 * std::min(dist_y, 6) + std::max(dist_x - 12, 0) +
2 * std::min(dist_x, 12));
} }
BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const