From df871def22832a46aa8415e6cbfcae5ad61d4f22 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 11 Aug 2026 15:03:04 +0200 Subject: [PATCH] xilinx: Small tweak to delay prediction Signed-off-by: gatecat --- himbaechel/uarch/xilinx/xilinx.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc index 6e9fdb77..951af93c 100644 --- a/himbaechel/uarch/xilinx/xilinx.cc +++ b/himbaechel/uarch/xilinx/xilinx.cc @@ -775,8 +775,12 @@ delay_t XilinxImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, int sx, sy, dx, dy; tile_xy(ctx->chip_info, src_bel.tile, sx, sy); tile_xy(ctx->chip_info, dst_bel.tile, dx, dy); + if (dst_pin == id_CIN && src_pin == id_CO3) + return 0; // TODO: improve sophistication here based on old nextpnr-xilinx code - return 500 + 25 * (2 * std::abs(dy - sy) + std::abs(dx - sx)); + int dist_x = std::abs(dx - sx), dist_y = std::abs(dy - sy); + return 500 + 12 * (2 * std::max(dist_y - 6, 0) + 4 * std::min(dist_y, 6) + std::max(dist_x - 12, 0) + + 2 * std::min(dist_x, 12)); } BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const