Update L2T4 model

This commit is contained in:
Miodrag Milanovic 2025-07-03 14:15:27 +02:00
parent 2d4042d3d5
commit 7e39bda445
6 changed files with 58 additions and 52 deletions

View File

@ -267,14 +267,11 @@ struct BitstreamBackend
case id_CPE_CPLINES.index:
case id_CPE_COMP.index:
case id_CPE_L2T4.index:
case id_CPE_L2T5.index:
case id_CPE_ADDF.index:
case id_CPE_ADDF2.index:
case id_CPE_MULT.index:
case id_CPE_MX4.index:
case id_CPE_EN_CIN.index:
case id_CPE_CONCAT.index:
case id_CPE_ADDCIN.index:
case id_CPE_FF.index:
case id_CPE_LATCH.index:
case id_CPE_RAMI.index:

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@ -33,7 +33,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
cell->ports[id].name = id;
cell->ports[id].type = dir;
};
if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_DUMMY)) {
if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_DUMMY)) {
add_port(id_IN1, PORT_IN);
add_port(id_IN2, PORT_IN);
add_port(id_IN3, PORT_IN);
@ -46,9 +46,10 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
add_port(id_PINY1, PORT_IN);
// For EN_CIN input
add_port(id_CINY1, PORT_IN);
if (type.in(id_CPE_LT_L, id_CPE_L2T5_L)) {
if (type.in(id_CPE_LT_L)) {
add_port(id_CINY2, PORT_IN);
add_port(id_PINY2, PORT_IN);
add_port(id_COMBIN, PORT_IN);
add_port(id_COUTX, PORT_OUT);
add_port(id_POUTX, PORT_OUT);

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@ -912,6 +912,8 @@ X(IN3)
X(IN4)
X(OUT)
X(CPOUT)
X(PINY1)
X(CINX)
// hardware primitive CPE_FF_U
X(CPE_FF_U)
@ -937,13 +939,14 @@ X(CPE_LT_L)
//X(IN2)
//X(IN3)
//X(IN4)
X(COMBIN)
//X(OUT)
//X(CPOUT)
X(MUXOUT)
X(CINX)
//X(CINX)
X(PINX)
X(CINY1)
X(PINY1)
//X(PINY1)
X(CINY2)
X(PINY2)
X(COUTX)
@ -2255,16 +2258,13 @@ X(CPE_LVDS_TOBUF)
X(CPE_LVDS_IOBUF)
X(CPE_L2T4)
X(CPE_L2T5)
X(CPE_L2T5_U)
X(CPE_L2T5_L)
X(CPE_ADDF)
X(CPE_ADDF2)
X(CPE_MULT)
X(CPE_MX4)
X(CPE_EN_CIN)
//X(CPE_EN_CIN)
X(CPE_CONCAT)
X(CPE_ADDCIN)
//X(CPE_ADDCIN)
X(CPE_DUMMY)
X(CPE_LATCH)
X(L2T4_UPPER)

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@ -202,11 +202,10 @@ void GateMateImpl::postPlace()
cell.second->params[id_INIT_L20] = Property(0b1100, 4);
}
cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1);
} else if (cell.second->type.in(id_CPE_L2T5_L, id_CPE_LT_L)) {
} else if (cell.second->type.in(id_CPE_LT_L)) {
BelId bel = cell.second->bel;
PlaceStrength strength = cell.second->belStrength;
uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
bool is_l2t5 = cell.second->type == id_CPE_L2T5_L;
Loc loc = ctx->getBelLocation(bel);
loc.z = CPE_LT_FULL_Z;
ctx->unbindBel(bel);
@ -223,34 +222,32 @@ void GateMateImpl::postPlace()
rename_param(cell.second.get(), id_INIT_L01, id_INIT_L03, 4);
rename_param(cell.second.get(), id_INIT_L10, id_INIT_L11, 4);
if (is_l2t5) {
cell.second->type = id_CPE_L2T5;
} else {
switch (func) {
case C_ADDF:
cell.second->type = id_CPE_ADDF;
break;
case C_ADDF2:
cell.second->type = id_CPE_ADDF2;
break;
case C_MULT:
cell.second->type = id_CPE_MULT;
break;
case C_MX4:
cell.second->type = id_CPE_MX4;
break;
case C_EN_CIN:
cell.second->type = id_CPE_EN_CIN;
break;
case C_CONCAT:
cell.second->type = id_CPE_CONCAT;
break;
case C_ADDCIN:
cell.second->type = id_CPE_ADDCIN;
break;
default:
break;
}
switch (func) {
case C_ADDF:
cell.second->type = id_CPE_ADDF;
break;
case C_ADDF2:
cell.second->type = id_CPE_ADDF2;
break;
case C_MULT:
cell.second->type = id_CPE_MULT;
break;
case C_MX4:
cell.second->type = id_CPE_MX4;
break;
case C_EN_CIN:
//cell.second->type = id_CPE_EN_CIN;
log_error("EN_CIN should be using L2T4.\n");
break;
case C_CONCAT:
cell.second->type = id_CPE_CONCAT;
break;
case C_ADDCIN:
log_error("ADDCIN should be using L2T4.\n");
//cell.second->type = id_CPE_ADDCIN;
break;
default:
break;
}
loc.z = CPE_LT_U_Z;
@ -274,7 +271,7 @@ void GateMateImpl::postPlace()
}
// Mark for deletion
else if (cell.second->type.in(id_CPE_L2T5_U, id_CPE_LT_U, id_CPE_DUMMY)) {
else if (cell.second->type.in(id_CPE_LT_U, id_CPE_DUMMY)) {
delete_cells.push_back(cell.second->name);
}
}
@ -343,7 +340,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const
if (cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF,
id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF))
return id_GPIO;
else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U))
else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4))
return id_CPE_LT;
else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF, id_CPE_LATCH))
return id_CPE_FF;
@ -372,9 +369,9 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
return cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF,
id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF);
else if (bel_type == id_CPE_LT_U)
return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_DUMMY);
return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_DUMMY);
else if (bel_type == id_CPE_LT_L)
return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_DUMMY);
return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_DUMMY);
else if (bel_type == id_CPE_FF_U)
return cell_type.in(id_CPE_FF_U, id_CPE_FF, id_CPE_LATCH);
else if (bel_type == id_CPE_FF_L)

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@ -63,6 +63,7 @@ struct GateMateImpl : HimbaechelAPI
bool isPipInverting(PipId pip) const override;
const GateMateTileExtraDataPOD *tile_extra_data(int tile) const;
void rename_param(CellInfo *cell, IdString name, IdString new_name, int width);
std::set<IdString> available_pads;
std::map<BelId, const PadInfoPOD *> bel_to_pad;
@ -81,7 +82,6 @@ struct GateMateImpl : HimbaechelAPI
void parse_ccf(const std::string &filename);
void assign_cell_info();
void rename_param(CellInfo *cell, IdString name, IdString new_name, int width);
void route_clock();
const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const;

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@ -149,7 +149,13 @@ void GateMatePacker::pack_cpe()
ci.renamePort(id_I3, id_IN4);
ci.renamePort(id_O, id_OUT);
ci.type = id_CPE_L2T5_L;
uarch->rename_param(&ci, id_INIT_L02, id_INIT_L00,4);
uarch->rename_param(&ci, id_INIT_L03, id_INIT_L01,4);
uarch->rename_param(&ci, id_INIT_L11, id_INIT_L10,4);
ci.cluster = ci.name;
ci.constr_abs_z = true;
ci.constr_z = CPE_LT_L_Z;
ci.type = id_CPE_L2T4;
} else if (ci.type == id_CC_MX2) {
ci.renamePort(id_D1, id_IN1);
NetInfo *sel = ci.getPort(id_S0);
@ -198,15 +204,20 @@ void GateMatePacker::pack_cpe()
}
for (auto ci : l2t5_list) {
CellInfo *upper = create_cell_ptr(id_CPE_L2T5_U, ctx->idf("%s$upper", ci->name.c_str(ctx)));
CellInfo *upper = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$upper", ci->name.c_str(ctx)));
upper->cluster = ci->name;
upper->constr_abs_z = false;
upper->constr_z = -1;
ci->cluster = ci->name;
upper->constr_abs_z = true;
upper->constr_z = CPE_LT_U_Z;
ci->movePortTo(id_I4, upper, id_IN1);
upper->params[id_INIT_L00] = Property(0b1010, 4);
upper->params[id_INIT_L10] = Property(0b1010, 4);
ci->constr_children.push_back(upper);
NetInfo *ci_out_conn = ctx->createNet(ctx->idf("%s$combin", ci->name.c_str(ctx)));
upper->connectPort(id_OUT, ci_out_conn);
ci->ports[id_COMBIN].name = id_COMBIN;
ci->ports[id_COMBIN].type = PORT_IN;
ci->connectPort(id_COMBIN, ci_out_conn);
}
l2t5_list.clear();