From 7e39bda445a14a3de057c4dfc2b26605c9e67fcf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 3 Jul 2025 14:15:27 +0200 Subject: [PATCH] Update L2T4 model --- himbaechel/uarch/gatemate/bitstream.cc | 3 -- himbaechel/uarch/gatemate/cells.cc | 5 +- himbaechel/uarch/gatemate/constids.inc | 14 +++--- himbaechel/uarch/gatemate/gatemate.cc | 65 ++++++++++++-------------- himbaechel/uarch/gatemate/gatemate.h | 2 +- himbaechel/uarch/gatemate/pack_cpe.cc | 21 +++++++-- 6 files changed, 58 insertions(+), 52 deletions(-) diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc index a5f4dc4b..3c2aa4dd 100644 --- a/himbaechel/uarch/gatemate/bitstream.cc +++ b/himbaechel/uarch/gatemate/bitstream.cc @@ -267,14 +267,11 @@ struct BitstreamBackend case id_CPE_CPLINES.index: case id_CPE_COMP.index: case id_CPE_L2T4.index: - case id_CPE_L2T5.index: case id_CPE_ADDF.index: case id_CPE_ADDF2.index: case id_CPE_MULT.index: case id_CPE_MX4.index: - case id_CPE_EN_CIN.index: case id_CPE_CONCAT.index: - case id_CPE_ADDCIN.index: case id_CPE_FF.index: case id_CPE_LATCH.index: case id_CPE_RAMI.index: diff --git a/himbaechel/uarch/gatemate/cells.cc b/himbaechel/uarch/gatemate/cells.cc index 3b5f62a6..0dda3d2c 100644 --- a/himbaechel/uarch/gatemate/cells.cc +++ b/himbaechel/uarch/gatemate/cells.cc @@ -33,7 +33,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) cell->ports[id].name = id; cell->ports[id].type = dir; }; - if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_DUMMY)) { + if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_DUMMY)) { add_port(id_IN1, PORT_IN); add_port(id_IN2, PORT_IN); add_port(id_IN3, PORT_IN); @@ -46,9 +46,10 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) add_port(id_PINY1, PORT_IN); // For EN_CIN input add_port(id_CINY1, PORT_IN); - if (type.in(id_CPE_LT_L, id_CPE_L2T5_L)) { + if (type.in(id_CPE_LT_L)) { add_port(id_CINY2, PORT_IN); add_port(id_PINY2, PORT_IN); + add_port(id_COMBIN, PORT_IN); add_port(id_COUTX, PORT_OUT); add_port(id_POUTX, PORT_OUT); diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc index 5a9f81b8..352361c5 100644 --- a/himbaechel/uarch/gatemate/constids.inc +++ b/himbaechel/uarch/gatemate/constids.inc @@ -912,6 +912,8 @@ X(IN3) X(IN4) X(OUT) X(CPOUT) +X(PINY1) +X(CINX) // hardware primitive CPE_FF_U X(CPE_FF_U) @@ -937,13 +939,14 @@ X(CPE_LT_L) //X(IN2) //X(IN3) //X(IN4) +X(COMBIN) //X(OUT) //X(CPOUT) X(MUXOUT) -X(CINX) +//X(CINX) X(PINX) X(CINY1) -X(PINY1) +//X(PINY1) X(CINY2) X(PINY2) X(COUTX) @@ -2255,16 +2258,13 @@ X(CPE_LVDS_TOBUF) X(CPE_LVDS_IOBUF) X(CPE_L2T4) -X(CPE_L2T5) -X(CPE_L2T5_U) -X(CPE_L2T5_L) X(CPE_ADDF) X(CPE_ADDF2) X(CPE_MULT) X(CPE_MX4) -X(CPE_EN_CIN) +//X(CPE_EN_CIN) X(CPE_CONCAT) -X(CPE_ADDCIN) +//X(CPE_ADDCIN) X(CPE_DUMMY) X(CPE_LATCH) X(L2T4_UPPER) diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index 4a206c55..8dc9e2a8 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -202,11 +202,10 @@ void GateMateImpl::postPlace() cell.second->params[id_INIT_L20] = Property(0b1100, 4); } cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1); - } else if (cell.second->type.in(id_CPE_L2T5_L, id_CPE_LT_L)) { + } else if (cell.second->type.in(id_CPE_LT_L)) { BelId bel = cell.second->bel; PlaceStrength strength = cell.second->belStrength; uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0); - bool is_l2t5 = cell.second->type == id_CPE_L2T5_L; Loc loc = ctx->getBelLocation(bel); loc.z = CPE_LT_FULL_Z; ctx->unbindBel(bel); @@ -223,34 +222,32 @@ void GateMateImpl::postPlace() rename_param(cell.second.get(), id_INIT_L01, id_INIT_L03, 4); rename_param(cell.second.get(), id_INIT_L10, id_INIT_L11, 4); - if (is_l2t5) { - cell.second->type = id_CPE_L2T5; - } else { - switch (func) { - case C_ADDF: - cell.second->type = id_CPE_ADDF; - break; - case C_ADDF2: - cell.second->type = id_CPE_ADDF2; - break; - case C_MULT: - cell.second->type = id_CPE_MULT; - break; - case C_MX4: - cell.second->type = id_CPE_MX4; - break; - case C_EN_CIN: - cell.second->type = id_CPE_EN_CIN; - break; - case C_CONCAT: - cell.second->type = id_CPE_CONCAT; - break; - case C_ADDCIN: - cell.second->type = id_CPE_ADDCIN; - break; - default: - break; - } + switch (func) { + case C_ADDF: + cell.second->type = id_CPE_ADDF; + break; + case C_ADDF2: + cell.second->type = id_CPE_ADDF2; + break; + case C_MULT: + cell.second->type = id_CPE_MULT; + break; + case C_MX4: + cell.second->type = id_CPE_MX4; + break; + case C_EN_CIN: + //cell.second->type = id_CPE_EN_CIN; + log_error("EN_CIN should be using L2T4.\n"); + break; + case C_CONCAT: + cell.second->type = id_CPE_CONCAT; + break; + case C_ADDCIN: + log_error("ADDCIN should be using L2T4.\n"); + //cell.second->type = id_CPE_ADDCIN; + break; + default: + break; } loc.z = CPE_LT_U_Z; @@ -274,7 +271,7 @@ void GateMateImpl::postPlace() } // Mark for deletion - else if (cell.second->type.in(id_CPE_L2T5_U, id_CPE_LT_U, id_CPE_DUMMY)) { + else if (cell.second->type.in(id_CPE_LT_U, id_CPE_DUMMY)) { delete_cells.push_back(cell.second->name); } } @@ -343,7 +340,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const if (cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF, id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF)) return id_GPIO; - else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U)) + else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4)) return id_CPE_LT; else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF, id_CPE_LATCH)) return id_CPE_FF; @@ -372,9 +369,9 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const return cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF, id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF); else if (bel_type == id_CPE_LT_U) - return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_DUMMY); + return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_DUMMY); else if (bel_type == id_CPE_LT_L) - return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_DUMMY); + return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_DUMMY); else if (bel_type == id_CPE_FF_U) return cell_type.in(id_CPE_FF_U, id_CPE_FF, id_CPE_LATCH); else if (bel_type == id_CPE_FF_L) diff --git a/himbaechel/uarch/gatemate/gatemate.h b/himbaechel/uarch/gatemate/gatemate.h index 5a648750..f63b38c6 100644 --- a/himbaechel/uarch/gatemate/gatemate.h +++ b/himbaechel/uarch/gatemate/gatemate.h @@ -63,6 +63,7 @@ struct GateMateImpl : HimbaechelAPI bool isPipInverting(PipId pip) const override; const GateMateTileExtraDataPOD *tile_extra_data(int tile) const; + void rename_param(CellInfo *cell, IdString name, IdString new_name, int width); std::set available_pads; std::map bel_to_pad; @@ -81,7 +82,6 @@ struct GateMateImpl : HimbaechelAPI void parse_ccf(const std::string &filename); void assign_cell_info(); - void rename_param(CellInfo *cell, IdString name, IdString new_name, int width); void route_clock(); const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const; diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index 154618b1..02e9a932 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -149,7 +149,13 @@ void GateMatePacker::pack_cpe() ci.renamePort(id_I3, id_IN4); ci.renamePort(id_O, id_OUT); - ci.type = id_CPE_L2T5_L; + uarch->rename_param(&ci, id_INIT_L02, id_INIT_L00,4); + uarch->rename_param(&ci, id_INIT_L03, id_INIT_L01,4); + uarch->rename_param(&ci, id_INIT_L11, id_INIT_L10,4); + ci.cluster = ci.name; + ci.constr_abs_z = true; + ci.constr_z = CPE_LT_L_Z; + ci.type = id_CPE_L2T4; } else if (ci.type == id_CC_MX2) { ci.renamePort(id_D1, id_IN1); NetInfo *sel = ci.getPort(id_S0); @@ -198,15 +204,20 @@ void GateMatePacker::pack_cpe() } for (auto ci : l2t5_list) { - CellInfo *upper = create_cell_ptr(id_CPE_L2T5_U, ctx->idf("%s$upper", ci->name.c_str(ctx))); + CellInfo *upper = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$upper", ci->name.c_str(ctx))); upper->cluster = ci->name; - upper->constr_abs_z = false; - upper->constr_z = -1; - ci->cluster = ci->name; + upper->constr_abs_z = true; + upper->constr_z = CPE_LT_U_Z; ci->movePortTo(id_I4, upper, id_IN1); upper->params[id_INIT_L00] = Property(0b1010, 4); upper->params[id_INIT_L10] = Property(0b1010, 4); ci->constr_children.push_back(upper); + + NetInfo *ci_out_conn = ctx->createNet(ctx->idf("%s$combin", ci->name.c_str(ctx))); + upper->connectPort(id_OUT, ci_out_conn); + ci->ports[id_COMBIN].name = id_COMBIN; + ci->ports[id_COMBIN].type = PORT_IN; + ci->connectPort(id_COMBIN, ci_out_conn); } l2t5_list.clear();