From 44a4d1e6cd567da481e60de8525d39933abfd741 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 4 Aug 2026 10:46:00 +0200 Subject: [PATCH] xilinx: don't use 'or' operator Signed-off-by: gatecat --- himbaechel/uarch/xilinx/fasm.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc index dc70320c..7cf5704a 100644 --- a/himbaechel/uarch/xilinx/fasm.cc +++ b/himbaechel/uarch/xilinx/fasm.cc @@ -1724,7 +1724,7 @@ struct FasmBackend // but in real life, Vivado sets AREG_0 is 0, // no bit is 1, and AREG_2 is 2 auto areg = int_or_default(ci->params, ctx->id("AREG"), 1); - if (areg == 0 or areg == 2) + if (areg == 0 || areg == 2) write_bit("AREG_" + std::to_string(areg)); auto ainput = str_or_default(ci->params, ctx->id("A_INPUT"), "DIRECT"); @@ -1735,7 +1735,7 @@ struct FasmBackend // but in real life, Vivado sets AREG_0 is 0, // no bit is 1, and AREG_2 is 2 auto breg = int_or_default(ci->params, ctx->id("BREG"), 1); - if (breg == 0 or breg == 2) + if (breg == 0 || breg == 2) write_bit("BREG_" + std::to_string(breg)); auto binput = str_or_default(ci->params, ctx->id("B_INPUT"), "DIRECT");