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gowin: Initial estimateDelay and ripup penalty (#1708) 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
myrtle 2026-04-30 08:07:11 +02:00 committed by GitHub
parent 0a8a848a72
commit 42e248b99e
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GPG Key ID: B5690EEEBB952194
2 changed files with 29 additions and 2 deletions
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6
himbaechel/arch.h
View File

@ -673,8 +673,8 @@ struct Arch : BaseArch<ArchRanges>
{ {
return uarch->predictDelay(src_bel, src_pin, dst_bel, dst_pin); return uarch->predictDelay(src_bel, src_pin, dst_bel, dst_pin);
} }
delay_t getDelayEpsilon() const override { return 20; } // TODO delay_t getDelayEpsilon() const override { return 20; } // TODO
delay_t getRipupDelayPenalty() const override { return 120; } // TODO delay_t getRipupDelayPenalty() const override { return ripup_penalty; } // TODO
float getDelayNS(delay_t v) const override { return v * 0.001; } float getDelayNS(delay_t v) const override { return v * 0.001; }
delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); } delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
uint32_t getDelayChecksum(delay_t v) const override { return v; } uint32_t getDelayChecksum(delay_t v) const override { return v; }
@ -909,6 +909,8 @@ struct Arch : BaseArch<ArchRanges>
bool fast_pip_delays = false; bool fast_pip_delays = false;
dict<WireId, uint64_t> drive_res; dict<WireId, uint64_t> drive_res;
dict<WireId, uint64_t> load_cap; dict<WireId, uint64_t> load_cap;
delay_t ripup_penalty = 120;
}; };
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END

25
himbaechel/uarch/gowin/gowin.cc
View File

@ -39,6 +39,8 @@ struct GowinImpl : HimbaechelAPI
bool isBelLocationValid(BelId bel, bool explain_invalid) const override; bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
void notifyBelChange(BelId bel, CellInfo *cell) override; void notifyBelChange(BelId bel, CellInfo *cell) override;
delay_t estimateDelay(WireId src, WireId dst) const override;
// Bel bucket functions // Bel bucket functions
IdString getBelBucketForCellType(IdString cell_type) const override; IdString getBelBucketForCellType(IdString cell_type) const override;
@ -118,6 +120,8 @@ struct GowinImpl : HimbaechelAPI
bool hclk_valid(BelId bel, IdString bel_type) const; bool hclk_valid(BelId bel, IdString bel_type) const;
array2d<std::vector<CellInfo *>> fast_logic_cell; array2d<std::vector<CellInfo *>> fast_logic_cell;
delay_t delay_m, delay_c;
}; };
struct GowinArch : HimbaechelArch struct GowinArch : HimbaechelArch
@ -248,6 +252,17 @@ void GowinImpl::init(Context *ctx)
if (args.options.count("disable_gp_clock_routing")) { if (args.options.count("disable_gp_clock_routing")) {
ctx->settings[id_NO_GP_CLOCK_ROUTING] = Property(1); ctx->settings[id_NO_GP_CLOCK_ROUTING] = Property(1);
} }
// configure delay estimates for A*
if (args.device.rfind("GW2A", 0) == 0 || args.device.rfind("GW5A", 0) == 0) {
delay_c = 300;
delay_m = 60;
ctx->ripup_penalty = 400;
} else {
delay_c = 600;
delay_m = 120;
ctx->ripup_penalty = 800;
}
} }
// We do not allow the use of global wires that bypass a special router. // We do not allow the use of global wires that bypass a special router.
@ -1679,6 +1694,16 @@ void GowinImpl::drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t
} }
} }
delay_t GowinImpl::estimateDelay(WireId src, WireId dst) const
{
int sx, sy, dx, dy;
tile_xy(ctx->chip_info, src.tile, sx, sy);
tile_xy(ctx->chip_info, dst.tile, dx, dy);
int dist_x = std::abs(dx - sx), dist_y = std::abs(dy - sy);
return delay_c + delay_m * (std::max(dist_x - 4, 0) + std::max(dist_y - 4, 0) +
2 * (std::min(dist_x, 4) + std::min(dist_y, 4)));
}
} // namespace } // namespace
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END