From 42a20eacb7cab91a2099e94a582910703ff8ee57 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 8 Jan 2026 16:04:34 +0100
Subject: [PATCH] wip

---
 himbaechel/uarch/gatemate/bitstream.cc    | 7 +++++++
 himbaechel/uarch/gatemate/extra_data.h    | 2 ++
 himbaechel/uarch/gatemate/gen/arch_gen.py | 6 +++++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index 813a69ae..45420b9c 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -153,6 +153,13 @@ struct BitstreamBackend
     void export_connection(ChipConfig &cc, PipId pip)
     {
         const auto &extra_data = *uarch->pip_extra_data(pip);
+        if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
+            IdString name = IdString(extra_data.name);
+            if (name==ctx->id("PASS")) {
+                auto n = ctx->getPipName(pip);
+                printf("PASS %s %s -> %s\n", n[0].c_str(ctx), n[2].c_str(ctx), n[1].c_str(ctx));
+            }
+        }
         if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) {
             IdString name = IdString(extra_data.name);
             CfgLoc loc = get_config_loc(pip.tile);
diff --git a/himbaechel/uarch/gatemate/extra_data.h b/himbaechel/uarch/gatemate/extra_data.h
index 066171b2..72401530 100644
--- a/himbaechel/uarch/gatemate/extra_data.h
+++ b/himbaechel/uarch/gatemate/extra_data.h
@@ -43,6 +43,8 @@ NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD {
     uint8_t plane;
     uint8_t dummy1;
     uint16_t dummy2;
+    uint32_t data;
+    uint32_t mask;
 });
 
 NPNR_PACKED_STRUCT(struct GateMateBelPinConstraintPOD {
diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
index 154f9530..b6dc9dd2 100644
--- a/himbaechel/uarch/gatemate/gen/arch_gen.py
+++ b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -74,6 +74,8 @@ class PipExtraData(BBAStruct):
     value: int = 0
     invert: int = 0
     plane: int = 0
+    data: int = 0
+    mask: int = 0
 
     def serialise_lists(self, context: str, bba: BBAWriter):
         pass
@@ -86,6 +88,8 @@ class PipExtraData(BBAStruct):
         bba.u8(self.plane)
         bba.u8(0)
         bba.u16(0)
+        bba.u32(self.data)
+        bba.u32(self.mask)
 
 @dataclass
 class BelPinConstraint(BBAStruct):
@@ -313,7 +317,7 @@ def main():
                     mux_flags |= MUX_ROUTING
                 if mux.name == "PASS":
                     mux_flags |= MUX_PASSTROUGH
-                pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane)
+                pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane, mux.data, mux.mask)
         if type_name in new_wires:
             for wire in sorted(new_wires[type_name]):
                 delay = wire_delay[wire]