mirror of https://github.com/YosysHQ/nextpnr.git
clangformat
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27395c73e7
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@ -633,7 +633,8 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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addProperty(topItem, QVariant::String, "Type", ctx->getBelType(bel).c_str(ctx));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkBelAvail(bel));
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addProperty(topItem, QVariant::String, "Bound Cell", ctx->nameOf(ctx->getBoundBelCell(bel)), ElementType::CELL);
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addProperty(topItem, QVariant::String, "Bound Cell Type", ctx->getBoundBelCell(bel) ? ctx->getBoundBelCell(bel)->type.c_str(ctx) : "");
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addProperty(topItem, QVariant::String, "Bound Cell Type",
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ctx->getBoundBelCell(bel) ? ctx->getBoundBelCell(bel)->type.c_str(ctx) : "");
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addProperty(topItem, QVariant::String, "Conflicting Cell", ctx->nameOf(ctx->getConflictingBelCell(bel)),
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ElementType::CELL);
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@ -33,8 +33,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
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cell->ports[id].name = id;
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cell->ports[id].type = dir;
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};
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if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L,
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id_CPE_DUMMY)) {
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if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_DUMMY)) {
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add_port(id_IN1, PORT_IN);
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add_port(id_IN2, PORT_IN);
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add_port(id_IN3, PORT_IN);
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@ -48,8 +47,8 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
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add_port(id_CINY2, PORT_IN);
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add_port(id_PINY2, PORT_IN);
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add_port(id_COUTX, PORT_OUT);
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add_port(id_POUTX, PORT_OUT);
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add_port(id_COUTX, PORT_OUT);
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add_port(id_POUTX, PORT_OUT);
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add_port(id_COUTY1, PORT_OUT);
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add_port(id_POUTY1, PORT_OUT);
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add_port(id_COUTY2, PORT_OUT);
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@ -97,8 +96,8 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
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add_port(id_CINY2, PORT_IN);
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add_port(id_PINY2, PORT_IN);
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add_port(id_COUTX, PORT_OUT);
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add_port(id_POUTX, PORT_OUT);
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add_port(id_COUTX, PORT_OUT);
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add_port(id_POUTX, PORT_OUT);
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add_port(id_COUTY1, PORT_OUT);
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add_port(id_POUTY1, PORT_OUT);
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add_port(id_COUTY2, PORT_OUT);
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@ -196,7 +196,8 @@ void GateMateImpl::postPlace()
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std::vector<IdString> delete_cells;
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for (auto &cell : ctx->cells) {
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/// TODO: Remove this section when pack_mult is cleaned
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if (cell.second->type.in(id_CPE_LT_L,id_CPE_LT_U) && int_or_default(cell.second->params, id_C_FUNCTION, 0)==0) {
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if (cell.second->type.in(id_CPE_LT_L, id_CPE_LT_U) &&
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int_or_default(cell.second->params, id_C_FUNCTION, 0) == 0) {
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (l.z == CPE_LT_L_Z) {
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if (!cell.second->params.count(id_INIT_L20))
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@ -411,7 +412,8 @@ struct GateMateArch : HimbaechelArch
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{
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return device.size() > 6 && device.substr(0, 6) == "CCGM1A";
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}
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std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args) override
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std::unique_ptr<HimbaechelAPI> create(const std::string &device,
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const dict<std::string, std::string> &args) override
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{
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return std::make_unique<GateMateImpl>();
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}
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@ -419,7 +419,6 @@ void GateMatePacker::pack_addf()
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ci_lower->connectPort(id_OUT, ci_out_conn);
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ci_cplines->connectPort(id_OUT1, ci_out_conn);
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NetInfo *ci_net = root->getPort(id_CI);
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if (ci_net->name == ctx->id("$PACKER_GND")) {
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ci_lower->params[id_INIT_L00] = Property(0b0000, 4);
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@ -327,8 +327,7 @@ void GateMatePacker::pack_io_sel()
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}
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std::vector<std::array<std::pair<CellInfo *, CellInfo *>, 9>> ddr(
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uarch->dies, std::array<std::pair<CellInfo *, CellInfo *>, 9>{}
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);
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uarch->dies, std::array<std::pair<CellInfo *, CellInfo *>, 9>{});
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auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
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NetInfo *clk_net = cell->getPort(id_CLK);
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if (clk_net) {
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