diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index 17e66e09..c14b7423 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -633,7 +633,8 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
         addProperty(topItem, QVariant::String, "Type", ctx->getBelType(bel).c_str(ctx));
         addProperty(topItem, QVariant::Bool, "Available", ctx->checkBelAvail(bel));
         addProperty(topItem, QVariant::String, "Bound Cell", ctx->nameOf(ctx->getBoundBelCell(bel)), ElementType::CELL);
-        addProperty(topItem, QVariant::String, "Bound Cell Type", ctx->getBoundBelCell(bel) ? ctx->getBoundBelCell(bel)->type.c_str(ctx) : "");
+        addProperty(topItem, QVariant::String, "Bound Cell Type",
+                    ctx->getBoundBelCell(bel) ? ctx->getBoundBelCell(bel)->type.c_str(ctx) : "");
         addProperty(topItem, QVariant::String, "Conflicting Cell", ctx->nameOf(ctx->getConflictingBelCell(bel)),
                     ElementType::CELL);
 
diff --git a/himbaechel/uarch/gatemate/cells.cc b/himbaechel/uarch/gatemate/cells.cc
index 045dc6b6..bf9ce225 100644
--- a/himbaechel/uarch/gatemate/cells.cc
+++ b/himbaechel/uarch/gatemate/cells.cc
@@ -33,8 +33,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
         cell->ports[id].name = id;
         cell->ports[id].type = dir;
     };
-    if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L,
-                id_CPE_DUMMY)) {
+    if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_DUMMY)) {
         add_port(id_IN1, PORT_IN);
         add_port(id_IN2, PORT_IN);
         add_port(id_IN3, PORT_IN);
@@ -48,8 +47,8 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
             add_port(id_CINY2, PORT_IN);
             add_port(id_PINY2, PORT_IN);
 
-            add_port(id_COUTX,  PORT_OUT);
-            add_port(id_POUTX,  PORT_OUT);
+            add_port(id_COUTX, PORT_OUT);
+            add_port(id_POUTX, PORT_OUT);
             add_port(id_COUTY1, PORT_OUT);
             add_port(id_POUTY1, PORT_OUT);
             add_port(id_COUTY2, PORT_OUT);
@@ -97,8 +96,8 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
         add_port(id_CINY2, PORT_IN);
         add_port(id_PINY2, PORT_IN);
 
-        add_port(id_COUTX,  PORT_OUT);
-        add_port(id_POUTX,  PORT_OUT);
+        add_port(id_COUTX, PORT_OUT);
+        add_port(id_POUTX, PORT_OUT);
         add_port(id_COUTY1, PORT_OUT);
         add_port(id_POUTY1, PORT_OUT);
         add_port(id_COUTY2, PORT_OUT);
diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
index 16144d98..0cd9d660 100644
--- a/himbaechel/uarch/gatemate/gatemate.cc
+++ b/himbaechel/uarch/gatemate/gatemate.cc
@@ -196,7 +196,8 @@ void GateMateImpl::postPlace()
     std::vector<IdString> delete_cells;
     for (auto &cell : ctx->cells) {
         /// TODO: Remove this section when pack_mult is cleaned
-        if (cell.second->type.in(id_CPE_LT_L,id_CPE_LT_U) && int_or_default(cell.second->params, id_C_FUNCTION, 0)==0) {
+        if (cell.second->type.in(id_CPE_LT_L, id_CPE_LT_U) &&
+            int_or_default(cell.second->params, id_C_FUNCTION, 0) == 0) {
             Loc l = ctx->getBelLocation(cell.second->bel);
             if (l.z == CPE_LT_L_Z) {
                 if (!cell.second->params.count(id_INIT_L20))
@@ -411,7 +412,8 @@ struct GateMateArch : HimbaechelArch
     {
         return device.size() > 6 && device.substr(0, 6) == "CCGM1A";
     }
-    std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args) override
+    std::unique_ptr<HimbaechelAPI> create(const std::string &device,
+                                          const dict<std::string, std::string> &args) override
     {
         return std::make_unique<GateMateImpl>();
     }
diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc
index f03637a0..4f86a456 100644
--- a/himbaechel/uarch/gatemate/pack_cpe.cc
+++ b/himbaechel/uarch/gatemate/pack_cpe.cc
@@ -419,7 +419,6 @@ void GateMatePacker::pack_addf()
         ci_lower->connectPort(id_OUT, ci_out_conn);
         ci_cplines->connectPort(id_OUT1, ci_out_conn);
 
-
         NetInfo *ci_net = root->getPort(id_CI);
         if (ci_net->name == ctx->id("$PACKER_GND")) {
             ci_lower->params[id_INIT_L00] = Property(0b0000, 4);
diff --git a/himbaechel/uarch/gatemate/pack_io.cc b/himbaechel/uarch/gatemate/pack_io.cc
index 737072f6..8875614f 100644
--- a/himbaechel/uarch/gatemate/pack_io.cc
+++ b/himbaechel/uarch/gatemate/pack_io.cc
@@ -327,8 +327,7 @@ void GateMatePacker::pack_io_sel()
     }
 
     std::vector<std::array<std::pair<CellInfo *, CellInfo *>, 9>> ddr(
-        uarch->dies, std::array<std::pair<CellInfo *, CellInfo *>, 9>{}
-    );
+            uarch->dies, std::array<std::pair<CellInfo *, CellInfo *>, 9>{});
     auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
         NetInfo *clk_net = cell->getPort(id_CLK);
         if (clk_net) {