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Cleanups

This commit is contained in:
Miodrag Milanovic 2025-07-07 09:37:08 +02:00
parent 054a652d4b
commit 1e76af0567
3 changed files with 8 additions and 4 deletions
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8
himbaechel/uarch/gatemate/constids.inc
View File

@ -942,7 +942,6 @@ X(CPE_LT_L)
X(COMBIN)
//X(OUT)
//X(CPOUT)
X(MUXOUT)
//X(CINX)
X(PINX)
X(CINY1)
@ -988,7 +987,7 @@ X(OUT1)
X(OUT2)
X(CPOUT1)
X(CPOUT2)
//X(MUXOUT)
X(MUXOUT)
//X(CINX)
//X(PINX)
//X(CINY1)
@ -1001,6 +1000,9 @@ X(CPOUT2)
//X(POUTY1)
//X(COUTY2)
//X(POUTY2)
//X(CLK)
//X(EN)
//X(SR)
// hardware primitive CPE_COMP
X(CPE_COMP)
@ -2268,3 +2270,5 @@ X(CPE_CONCAT)
X(CPE_DUMMY)
X(CPE_LATCH)
X(L2T4_UPPER)
X(CPE_MX8)
X(CPE_BRIDGE)

2
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -18,7 +18,6 @@
*/
#include "gatemate.h"
#include "design_utils.h"
#include "log.h"
#include "placer_heap.h"
@ -289,7 +288,6 @@ void GateMateImpl::preRoute() { route_clock(); }
void GateMateImpl::postRoute()
{
ctx->assignArchInfo();
print_utilisation(ctx);
const ArchArgs &args = ctx->args;
if (args.options.count("out")) {

2
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -268,6 +268,8 @@ def main():
tt.create_wire(wire.name, wire.type)
for prim in sorted(die.get_primitives_for_type(type_name)):
bel = tt.create_bel(prim.name, prim.type, prim.z)
if (prim.name in ["CPE_LT_FULL"]):
bel.flags |= BEL_FLAG_HIDDEN
extra = BelExtraData()
for constr in sorted(die.get_pins_constraint(type_name, prim.name, prim.type)):
extra.add_constraints(ch.strs.id(constr.name),constr.rel_x,constr.rel_y,4 if constr.pin_num==2 else 5)