From 1e76af056787bc392016cdec1306686722561de7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 7 Jul 2025 09:37:08 +0200
Subject: [PATCH] Cleanups

---
 himbaechel/uarch/gatemate/constids.inc    | 8 ++++++--
 himbaechel/uarch/gatemate/gatemate.cc     | 2 --
 himbaechel/uarch/gatemate/gen/arch_gen.py | 2 ++
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc
index 352361c5..d68a5196 100644
--- a/himbaechel/uarch/gatemate/constids.inc
+++ b/himbaechel/uarch/gatemate/constids.inc
@@ -942,7 +942,6 @@ X(CPE_LT_L)
 X(COMBIN)
 //X(OUT)
 //X(CPOUT)
-X(MUXOUT)
 //X(CINX)
 X(PINX)
 X(CINY1)
@@ -988,7 +987,7 @@ X(OUT1)
 X(OUT2)
 X(CPOUT1)
 X(CPOUT2)
-//X(MUXOUT)
+X(MUXOUT)
 //X(CINX)
 //X(PINX)
 //X(CINY1)
@@ -1001,6 +1000,9 @@ X(CPOUT2)
 //X(POUTY1)
 //X(COUTY2)
 //X(POUTY2)
+//X(CLK)
+//X(EN)
+//X(SR)
 
 // hardware primitive CPE_COMP
 X(CPE_COMP)
@@ -2268,3 +2270,5 @@ X(CPE_CONCAT)
 X(CPE_DUMMY)
 X(CPE_LATCH)
 X(L2T4_UPPER)
+X(CPE_MX8)
+X(CPE_BRIDGE)
diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
index 751d6468..35f6e2d4 100644
--- a/himbaechel/uarch/gatemate/gatemate.cc
+++ b/himbaechel/uarch/gatemate/gatemate.cc
@@ -18,7 +18,6 @@
  */
 
 #include "gatemate.h"
-#include "design_utils.h"
 #include "log.h"
 #include "placer_heap.h"
 
@@ -289,7 +288,6 @@ void GateMateImpl::preRoute() { route_clock(); }
 void GateMateImpl::postRoute()
 {
     ctx->assignArchInfo();
-    print_utilisation(ctx);
 
     const ArchArgs &args = ctx->args;
     if (args.options.count("out")) {
diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
index adafb539..5949610e 100644
--- a/himbaechel/uarch/gatemate/gen/arch_gen.py
+++ b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -268,6 +268,8 @@ def main():
             tt.create_wire(wire.name, wire.type)
         for prim in sorted(die.get_primitives_for_type(type_name)):
             bel = tt.create_bel(prim.name, prim.type, prim.z)
+            if (prim.name in ["CPE_LT_FULL"]):
+                bel.flags |= BEL_FLAG_HIDDEN     
             extra = BelExtraData()
             for constr in sorted(die.get_pins_constraint(type_name, prim.name, prim.type)):
                 extra.add_constraints(ch.strs.id(constr.name),constr.rel_x,constr.rel_y,4 if constr.pin_num==2 else 5)